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Kernel DRM miscellaneous fixes and cross-tree changes
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cache-l2x0.c
Age
Commit message (
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)
Author
Files
Lines
2011-03-16
Merge branch 'misc' into devel
Russell King
1
-14
/
+18
2011-03-09
ARM: 6795/1: l2x0: Errata fix for flush by Way operation can cause data corrupti
Santosh Shilimkar
1
-14
/
+18
2011-02-19
ARM: 6741/1: errata: pl310 cache sync operation may be faulty
Srinidhi Kasagar
1
-0
/
+6
2010-10-26
ARM: l2x0: Optimise the range based operations
Santosh Shilimkar
1
-0
/
+22
2010-10-26
ARM: l2x0: Determine the cache size
Santosh Shilimkar
1
-2
/
+11
2010-10-26
arm: Implement l2x0 cache disable functions
Thomas Gleixner
1
-1
/
+27
2010-10-26
ARM: Improve the L2 cache performance when PL310 is used
Catalin Marinas
1
-3
/
+12
2010-07-29
ARM: 6272/1: Convert L2x0 to use the IO relaxed operations
Catalin Marinas
1
-13
/
+13
2010-07-09
ARM: 6210/1: Do not rely on reset defaults of L2X0_AUX_CTRL
Sascha Hauer
1
-2
/
+3
2010-05-17
Merge branch 'devel-stable' into devel
Russell King
1
-0
/
+10
2010-05-15
ARM: 6094/1: Extend cache-l2x0 to support the 16-way PL310
Jason McMullan
1
-5
/
+34
2010-03-25
ARM: 5995/1: ARM: Add L2x0 outer_sync() support (3/4)
Catalin Marinas
1
-0
/
+10
2010-02-15
ARM: 5919/1: ARM: L2 : Errata 588369: Clean & Invalidate do not invalidate cl...
Santosh Shilimkar
1
-0
/
+36
2010-02-15
ARM: 5916/1: ARM: L2 : Add maintainace by line helper functions
Santosh Shilimkar
1
-10
/
+26
2009-12-14
Merge branch 'pending-l2x0' into cache
Russell King
1
-21
/
+72
2009-12-14
ARM: cache-l2x0: make better use of background cache handling
Russell King
1
-11
/
+23
2009-12-14
ARM: cache-l2x0: avoid taking spinlock for every iteration
Russell King
1
-13
/
+52
2009-12-03
ARM: 5845/1: l2x0: check whether l2x0 already enabled
Srinidhi Kasagar
1
-9
/
+16
2008-09-06
[ARM] Convert asm/io.h to linux/io.h
Russell King
1
-1
/
+1
2007-09-17
[ARM] 4568/1: fix l2x0 cache invalidate handling of unaligned addresses
Rui Sousa
1
-1
/
+11
2007-07-20
[ARM] 4500/1: Add locking around the background L2x0 cache operations
Catalin Marinas
1
-0
/
+6
2007-02-11
[ARM] 4135/1: Add support for the L210/L220 cache controllers
Catalin Marinas
1
-0
/
+104