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2012-01-09Merge tag 'drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-socLinus Torvalds1-5/+5
Driver specific changes Again, a lot of platforms have changes in here: pxa, samsung, omap, at91, imx, ... * tag 'drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (54 commits) ARM: sa1100: clean up of the clock support ARM: pxa: add dummy clock for sa1100-rtc RTC: sa1100: support sa1100, pxa and mmp soc families RTC: sa1100: remove redundant code of setting alarm RTC: sa1100: Clean out ost register Input: zylonite-wm97xx - replace IRQ_GPIO() with gpio_to_irq() pcmcia: pxa: replace IRQ_GPIO() with gpio_to_irq() ARM: EXYNOS: Modified files for SPI consolidation work ARM: S5P64X0: Enable SDHCI support ARM: S5P64X0: Add lookup of sdhci-s3c clocks using generic names ARM: S5P64X0: Add HSMMC setup for host Controller ARM: EXYNOS: Add USB OHCI support to ORIGEN board USB: Add Samsung Exynos OHCI diver ARM: EXYNOS: Add USB OHCI support to SMDKV310 board ARM: EXYNOS: Add USB OHCI device net: macb: fix build break with !CONFIG_OF i2c: tegra: Support DVC controller in device tree i2c: tegra: Add __devinit/exit to probe/remove net/at91_ether: use gpio_is_valid for phy IRQ line ARM: at91/net: add macb ethernet controller in 9g45/9g20 DT ...
2011-12-16ARM: OMAP4: clock: Add CPU local timer clock nodeSantosh Shilimkar1-0/+9
Local timer clock is sourced from the CPU clock and hence changes along with CPU clock. These per CPU local timers are used as clock-events, so they need to be reconfigured on CPU frequency change as part of CPUfreq governor. Newly introduced clockevents_reconfigure() needs to know the twd clock-rate. Provide a clock-node to make clk_get_rate() work for TWD. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Cc: Paul Walmsley <paul@pwsan.com> Cc: Kevin Hilman <khilman@ti.com> [paul@pwsan.com: renamed clock node to 'mpu_periphclk' to indicate that this is the Cortex-A9 MPCore subsystem clock PERIPHCLK (DDI 0407G); moved clock and clkdev entries to match the autogenerated script output] Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2011-12-16ARM: OMAP: USB: device name change for the clk names of usbhsKeshava Munegowda1-5/+5
device name usbhs clocks are changed from usbhs-omap.0 to usbhs_omap; this is because in the hwmod registration the device name is set as usbhs_omap; The redudant clock nodes are removed. Signed-off-by: Keshava Munegowda <keshava_mgowda@ti.com> Reviewed-by: Partha Basak <parthab@india.ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
2011-11-04ARM: OMAP2+: clock data: Remove redundant timer clkdevBenoit Cousson1-11/+0
The commit 318c3e15cd55c73a26ae22a65a8183655b3003f9 added some "fck" clock alias to timer devices that are not needed anymore since hwmod framework will create them automatically. A warning was added to highlight and thus fix the redundancy. [ 0.616424] omap_timer.1: alias fck already exists [ 0.621948] omap_timer.2: alias fck already exists [ 0.627380] omap_timer.3: alias fck already exists [ 0.632781] omap_timer.4: alias fck already exists [ 0.638214] omap_timer.5: alias fck already exists [ 0.643615] omap_timer.6: alias fck already exists [ 0.649078] omap_timer.7: alias fck already exists [ 0.654479] omap_timer.8: alias fck already exists [ 0.659881] omap_timer.9: alias fck already exists [ 0.665283] omap_timer.10: alias fck already exists [ 0.670776] omap_timer.11: alias fck already exists Remove all the clkdev entries for timer fck alias. Signed-off-by: Benoit Cousson <b-cousson@ti.com> Cc: Tarun Kanti DebBarma <tarun.kanti@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2011-11-04Merge branch 'omap_clock_fixes_3.2' of git://git.pwsan.com/linux-2.6 into fixesTony Lindgren1-9/+23
2011-10-07ARM: OMAP4: clock: Add missing clock divider for OCP_ABE_ICLKJon Hunter1-1/+15
The parent clock of the OCP_ABE_ICLK is the AESS_FCLK and the parent clock of the AESS_FCLK is the ABE_FCLK... ABE_FCLK --> AESS_FCLK --> OCP_ABE_ICLK The AESS_FCLK and OCP_ABE_ICLK clocks both have dividers which determine their operational frequency. However, the dividers for the AESS_FCLK and OCP_ABE_ICLK are controlled via a single bit, which is the CM1_ABE_AESS_CLKCTRL[24] bit. When this bit is set to 0, the AESS_FCLK divider is 1 and the OCP_ABE_ICLK divider is 2. Similarly, when this bit is set to 1, the AESS_FCLK divider is 2 and the OCP_ABE_ICLK is 1. The above relationship between the AESS_FCLK and OCP_ABE_ICLK dividers ensure that the OCP_ABE_ICLK clock is always half the frequency of the ABE_CLK... OCP_ABE_ICLK = ABE_FCLK/2 The divider for the OCP_ABE_ICLK is currently missing so add a divider that will ensure the OCP_ABE_ICLK frequency is always half the ABE_FCLK frequency. Signed-off-by: Jon Hunter <jon-hunter@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
2011-10-07ARM: OMAP4460: Clock: Adding support for 4460 specific clocksPaul Walmsley1-6/+6
OMAP4460 specific clocks are not getting added as the cpu_is_omap44xx is choosing only OMAP4430 specific clock nodes. Changing it to add to OMAP4460 specific clocks also. This is clocks are required of temperature sensor. Signed-off-by: Vishwanath BS <vishwanath.bs@ti.com> Signed-off-by: Keerthy <j-keerthy@ti.com> Cc: paul@pwsan.com [paul@pwsan.com: updated to apply] Signed-off-by: Paul Walmsley <paul@pwsan.com>
2011-10-07ARM: OMAP4: clock: round_rate and recalc functions for DPLL_ABEMike Turquette1-2/+2
OMAP4 DPLL_ABE can enable a 4X multipler on top of the normal MN multipler and divider. This is achieved by setting CM_CLKMODE_DPLL_ABE.DPLL_REGM4XEN bit in CKGEN module of CM1. From the OMAP4 TRM: Fdpll = Fref x 2 x (4 x M/(N+1)) in case REGM4XEN bit field is set (only applicable to DPLL_ABE). Add new round_rate() and recalc() functions for OMAP4, that check the setting of REGM4XEN bit and handle this appropriately. The new functions are a simple wrapper on top of the existing omap2_dpll_round_rate() and omap2_dpll_get_rate() functions to handle the REGM4XEN bit. The REGM4XEN bit is only implemented for the ABE DPLL on OMAP4 and so only dpll_abe_ck uses omap4_dpll_regm4xen_round_rate() and omap4_dpll_regm4xen_recalc() functions. Signed-off-by: Mike Turquette <mturquette@ti.com> Tested-by: Jon Hunter <jon-hunter@ti.com> Signed-off-by: Jon Hunter <jon-hunter@ti.com> [paul@pwsan.com: fixed attempt to return a negative from a fn returning unsigned; pass along errors from omap2_dpll_round_rate(); added documentation; added Jon's S-o-b] Signed-off-by: Paul Walmsley <paul@pwsan.com>
2011-09-21ARM: OMAP2+: dmtimer: add device names to flck nodesTarun Kanti DebBarma1-0/+33
Add device name to OMAP2 dmtimer fclk nodes so that the fclk nodes can be retrieved by doing a clk_get with the corresponding device pointers or device names. Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Tarun Kanti DebBarma <tarun.kanti@ti.com> Signed-off-by: Thara Gopinath <thara@ti.com> Acked-by: Cousson, Benoit <b-cousson@ti.com> [tony@atomide.com: fixed typo in email address] Signed-off-by: Tony Lindgren <tony@atomide.com>
2011-09-04Merge branches 'non_hwmod_compliant_fix_3.1rc', 'omap3_clock_fixes_3.1rc', ↵Paul Walmsley1-0/+2
'omap4_clock_fixes_3.1rc', 'missing_2430_musb_adds_terminator_fix_3.1rc' and 'pwrdm_clkdm_fixes_3.1rc' into prcm-fixes-a-3.1rc
2011-08-21OMAP4: clock: fix compile warningPaul Walmsley1-0/+2
Fix the following compile warning: arch/arm/mach-omap2/clock44xx_data.c: In function 'omap4xxx_clk_init': arch/arm/mach-omap2/clock44xx_data.c:3371:6: warning: 'cpu_clkflg' may be used uninitialized in this function The approach taken here is intended to work if omap4xxx_clk_init() is converted into an initcall. Thanks to Bjarne Steinsbo <bsteinsbo@gmail.com> for proposing another approach. Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Bjarne Steinsbo <bsteinsbo@gmail.com>
2011-08-19OMAP4: clock: re-enable previous clockdomain enable/disable sequencePaul Walmsley1-1/+7
After commit 665d001338b494d6d62810aa99b4c0fa1a0884b9 ("OMAP2+: hwmod: Follow the recommended PRCM module enable sequence"), device drivers for OMAP IP blocks that do not use runtime PM can cause oopses or kernel instability[1][2]. This is because those non-runtime PM drivers do not use the hwmod code, which implements the correct IP block enable and disable sequence. Several options for dealing with this problem have been proposed: 1. Add a new field to the OMAP struct clk to mark clocks that are currently used by non-runtime PM drivers. Modify the clock code to use the old clockdomain sequence for these marked clocks. As drivers are converted to use runtime PM, remove the annotation from the clocks. 2. Similar to #1, but associate the flag with the struct omap_clk instead. 3. Add IDLEST wait support to the OMAP4 clock code, similar to the way it is implemented for OMAP2/3, and enable it in each struct clk currently used by non-runtime PM drivers. As drivers are converted to use runtime PM, remove the annotation from the clocks. 4. Do nothing; leave the problem to those responsible for the unconverted drivers. 5. Re-enable clock-based clockdomain control in the OMAP4 clock code. This would revert back to the behavior of Linux 3.0, simply with a slightly longer module enable/disable latency. Unfortunately, no approach seemed particularly good. Options 1 through 3 seemed unwise due to the following reasons: A. The OMAP struct clks are intended primarily to describe hardware clock nodes, and the intention is that no driver-specific data should be stored there (applies to #1) B. The resulting patch would have been quite large for the -rc series (applies to #1, #2, #3) C. The patch would have been a new, yet temporary hack; and similar fixes have drawn negative comments in the recent past (see for example [3]) Option 4 is undesirable because commit 665d001338b494d6d62810aa99b4c0fa1a0884b9 ("OMAP2+: hwmod: Follow the recommended PRCM module enable sequence") has resulted in a less stable kernel; and kernel stability is more important than OMAP4 power management. Option 5 is the approach taken in this patch. This seemed to be the least intrusive approach for 3.1-rc. The approach in this patch was originally proposed by Ohad Ben-Cohen <ohad@wizery.com>. I'm simply writing the commit message and passing it along. ... Thanks to Luciano Coelho <coelho@ti.com> for reporting the problem. Thanks to Ohad Ben-Cohen <ohad@wizery.com> for tracking the problem down, generating a temporary workaround, and proposing a patch to deal with the problem. Thanks to Rajendra Nayak <rnayak@ti.com> for proposing another patch to deal with the problem. Thanks to Felipe Balbi <balbi@ti.com> for comments. 1. Coelho, Luciano <coelho@ti.com>. _Re: Oops on ehci_hcd when booting 3.0.0-rc2 on panda_. Tue, 09 Aug 2011 14:26:08 +0300. Posted to the <linux-omap@vger.kernel.org> mailing list. Available from (among others) http://www.spinics.net/linux/lists/linux-omap/msg55213.html 2. Munegowda, Keshava <keshava_mgowda@ti.com>. _Re: Oops on ehci_hcd when booting 3.0.0-rc2 on panda_. Thu, 11 Aug 2011 13:51:05 +0530. Posted to the <linux-omap@vger.kernel.org> mailing list. Available from (among others) http://www.spinics.net/linux/lists/linux-omap/msg55371.html 3. King, Russell <linux@arm.linux.org.uk>. _Re: [PATCH 5/8] OMAP4: PM: TEMP: Prevent l3init from idling/force sleep_. Thu, 23 Jun 2011 16:22:49 +0100. Posted to the <linux-omap@vger.kernel.org> mailing list. Available from (among others) http://www.mail-archive.com/linux-omap@vger.kernel.org/msg51392.html Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Luciano Coelho <coelho@ti.com> Cc: Ohad Ben-Cohen <ohad@wizery.com> Cc: Rajendra Nayak <rnayak@ti.com> Cc: Benoît Cousson <b-cousson@ti.com> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
2011-07-26Merge branch 'next/devel2' of ↵Linus Torvalds1-43/+172
git://git.kernel.org/pub/scm/linux/kernel/git/arm/linux-arm-soc * 'next/devel2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/linux-arm-soc: (47 commits) OMAP: Add debugfs node to show the summary of all clocks OMAP2+: hwmod: Follow the recommended PRCM module enable sequence OMAP2+: clock: allow per-SoC clock init code to prevent clockdomain calls from clock code OMAP2+: clockdomain: Add per clkdm lock to prevent concurrent state programming OMAP2+: PM: idle clkdms only if already in idle OMAP2+: clockdomain: add clkdm_in_hwsup() OMAP2+: clockdomain: Add 2 APIs to control clockdomain from hwmod framework OMAP: clockdomain: Remove redundant call to pwrdm_wait_transition() OMAP4: hwmod: Introduce the module control in hwmod control OMAP4: cm: Add two new APIs for modulemode control OMAP4: hwmod data: Add modulemode entry in omap_hwmod structure OMAP4: hwmod data: Add PRM context register offset OMAP4: prm: Remove deprecated functions OMAP4: prm: Replace warm reset API with the offset based version OMAP4: hwmod: Replace RSTCTRL absolute address with offset macros OMAP: hwmod: Wait the idle status to be disabled OMAP4: hwmod: Replace CLKCTRL absolute address with offset macros OMAP2+: hwmod: Init clkdm field at boot time OMAP4: hwmod data: Add clock domain attribute OMAP4: clock data: Add missing divider selection for auxclks ...
2011-07-26Merge branch 'next/fixes2' of ↵Linus Torvalds1-4/+5
git://git.kernel.org/pub/scm/linux/kernel/git/arm/linux-arm-soc * 'next/fixes2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/linux-arm-soc: (24 commits) ASoC: omap: McBSP: fix build breakage on OMAP1 OMAP: hwmod: fix the i2c-reset timeout during bootup I2C: OMAP2+: add correct functionality flags to all omap2plus i2c dev_attr I2C: OMAP2+: Tag all OMAP2+ hwmod defintions with I2C IP revision I2C: OMAP1/OMAP2+: create omap I2C functionality flags for each cpu_... test I2C: OMAP2+: Introduce I2C IP versioning constants I2C: OMAP2+: increase omap_i2c_dev_attr flags from u8 to u32 I2C: OMAP2+: Set hwmod flags to only allow 16-bit accesses to i2c OMAP4: hwmod data: Change DSS main_clk scheme OMAP4: powerdomain data: Remove unsupported MPU powerdomain state OMAP4: clock data: Keep GPMC clocks always enabled and hardware managed OMAP4: powerdomain data: Fix core mem states and missing cefuse flag OMAP2+: PM: Initialise sleep_switch to a non-valid value OMAP4: hwmod data: Modify DSS opt clocks OMAP4: iommu: fix clock name omap: iovmm: s/sg_dma_len(sg)/sg->length/ omap: iommu: fix pte programming arm: omap3: cm-t35: fix slow path warning arm: omap3: cm-t35: minor comments fixes omap: ZOOM: QUART: Request reset GPIO ...
2011-07-26Merge branch 'next/soc' of ↵Linus Torvalds1-0/+39
git://git.kernel.org/pub/scm/linux/kernel/git/arm/linux-arm-soc * 'next/soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/linux-arm-soc: MAINTAINERS: add maintainer of CSR SiRFprimaII machine ARM: CSR: initializing L2 cache ARM: CSR: mapping early DEBUG_LL uart ARM: CSR: Adding CSR SiRFprimaII board support OMAP4: clocks: Update the clock tree with 4460 clock nodes OMAP4: PRCM: OMAP4460 specific PRM and CM register bitshifts OMAP4: ID: add omap_has_feature for max freq supported OMAP: ID: introduce chip detection for OMAP4460 ARM: Xilinx: merge board file into main platform code ARM: Xilinx: Adding Xilinx board support Fix up conflicts in arch/arm/mach-omap2/cm-regbits-44xx.h
2011-07-10Merge branches 'omap4_clockdomain_hwmod_3.1', 'clock_debugfs_a_3.1', ↵Paul Walmsley1-43/+171
'omap4_clock_auxclk_3.1' and 'omap_device_a_3.1' into prcm-devel-3.1
2011-07-10OMAP2+: hwmod: Follow the recommended PRCM module enable sequenceRajendra Nayak1-0/+1
On OMAP4, the PRCM recommended sequence for enabling a module after power-on-reset is: -1- Force clkdm to SW_WKUP -2- Enabling the clocks -3- Configure desired module mode to "enable" or "auto" -4- Wait for the desired module idle status to be FUNC -5- Program clkdm in HW_AUTO(if supported) This sequence applies to all older OMAPs' as well, however since they use autodeps, it makes sure that no clkdm is in IDLE, and hence not requiring a force SW_WKUP when a module is being enabled. OMAP4 does not need to support autodeps, because of the dyanamic dependency feature, wherein the HW takes care of waking up a clockdomain from idle and hence the module, whenever an interconnect access happens to the given module. Implementing the sequence for OMAP4 requires the clockdomain handling that is currently done in clock framework to be done as part of hwmod framework since the step -4- above to "Wait for the desired module idle status to be FUNC" is done as part of hwmod framework. Signed-off-by: Rajendra Nayak <rnayak@ti.com> [b-cousson@ti.com: Adapt it to the new clkdm hwmod attribute and API] Signed-off-by: Benoit Cousson <b-cousson@ti.com> Cc: Paul Walmsley <paul@pwsan.com> [paul@pwsan.com: dropped mach-omap2/clock.c changes; modified to only call the clockdomain code if oh->clkdm is set; disable clock->clockdomain interaction on OMAP4] Signed-off-by: Paul Walmsley <paul@pwsan.com>
2011-07-10OMAP4: clock data: Add missing divider selection for auxclksRajendra Nayak1-24/+152
On OMAP4 the auxclk nodes (part of SCRM) support both divider as well as parent selection. Supporting this requires splitting the existing nodes (which support only parent selection) into two nodes, one for parent and another for divider selection. The nodes for parent selection are named auxclk*_src_ck and the ones for divider selection as auxclk*_ck. Signed-off-by: Rajendra Nayak <rnayak@ti.com> [b-cousson@ti.com: Rebase on top of clock cleanup and autogen alignement] Signed-off-by: Benoit Cousson <b-cousson@ti.com> Cc: Paul Walmsley <paul@pwsan.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
2011-07-10OMAP: omap_device: Create clkdev entry for hwmod main_clkBenoit Cousson1-19/+19
Extend the existing function to create clkdev for every optional clocks to add a well one "fck" alias for the main_clk of the omap_hwmod. It will allow to remove these static clkdev entries from the clockXXX_data.c file. Signed-off-by: Benoit Cousson <b-cousson@ti.com> Cc: Paul Walmsley <paul@pwsan.com> Cc: Kevin Hilman <khilman@ti.com> Cc: Todd Poynor <toddpoynor@google.com> [paul@pwsan.com: remove all of the "fck" role clkdev aliases from the clock data files; fixed error message] Signed-off-by: Paul Walmsley <paul@pwsan.com>
2011-07-10Merge branches 'powerdomain_fixes_3.1', 'hardware_workarounds_3.1', ↵Paul Walmsley1-165/+81
'hwmod_dss_fix_3.1' and 'i2c_fixes_3.1' into prcm-fixes-3.1
2011-07-09OMAP4: clock data: Keep GPMC clocks always enabled and hardware managedSantosh Shilimkar1-0/+1
On OMAP4, CPU accesses on unmapped addresses are redirected to GPMC by L3 interconnect. Because of CPU speculative nature, such accesses are possible which can lead to indirect access to GPMC and if it's clock is not running, it can result in hang/abort on the platform. Above makes access to GPMC unpredictable during the execution, so it's module mode needs to be kept under hardware control instead of software control. Since the auto gating is supported for GPMC, there isn't any power impact because of this change. The issue was un-covered with security middleware running along with HLOS. In this case GPMC had a valid MMU descriptor on secure side where as HLOS didn't map the GMPC because it isn't being used. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> [b-cousson@ti.com: Update subject and fix typos in the changelog] Signed-off-by: Benoit Cousson <b-cousson@ti.com> Cc: Kevin Hilman <khilman@ti.com> Cc: Rajendra Nayak <rnayak@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
2011-07-09OMAP4: hwmod data: Modify DSS opt clocksTomi Valkeinen1-4/+4
Add missing DSS optional clocks to HWMOD data for OMAP4xxx. Add HWMOD_CONTROL_OPT_CLKS_IN_RESET flag for dispc to fix dispc reset. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> [b-cousson@ti.com: Remove a comment and update the subject] Signed-off-by: Benoit Cousson <b-cousson@ti.com> Cc: Tomi Valkeinen <tomi.valkeinen@ti.com> [paul@pwsan.com: removed DSS "fck" role and some clkdev aliases at Tomi's request] Signed-off-by: Paul Walmsley <paul@pwsan.com>
2011-07-09OMAP4: clock data: Remove UNIPRO clock nodesJon Hunter1-60/+0
UNIPRO was removed from OMAP4 devices from ES2.0 onwards. Since this IP was anyway non-functional and not supported, it is best to remove it completely. Signed-off-by: Jon Hunter <jon-hunter@ti.com> [b-cousson@ti.com: Update the changelog] Signed-off-by: Benoit Cousson <b-cousson@ti.com> [paul@pwsan.com: split PRCM header file changes into a separate patch] Signed-off-by: Paul Walmsley <paul@pwsan.com>
2011-07-09OMAP4: clock data: Remove McASP2, McASP3 and MMC6 clocksJon Hunter1-55/+31
McASP2, 3 and MMC6 modules are not present in the OMAP4 family. Remove the fclk and the clksel related to these nodes. Rename the references that were potentially re-used in order nodes. Remove related macros in prcm header files. Update TI copyright date. Signed-off-by: Jon Hunter <jon-hunter@ti.com> [b-cousson@ti.com: Update the patch according to autogen output] Signed-off-by: Benoit Cousson <b-cousson@ti.com> [paul@pwsan.com: split PRCM data changes into a separate patch] Signed-off-by: Paul Walmsley <paul@pwsan.com>
2011-07-09OMAP4: clock data: Fix max mult and div for USB DPLLBenoit Cousson1-15/+14
The DPLL USB can generate higher speed (x2) than the regular ones. The max multiplication value is then twice the previous value. Fix both max_mult and max_div with that correct values. Change the max_div variable type to u16 to allow storing up to 256. Replace as well the define with the value to avoid unneeded indirection and provide a better readability. Remove the defines that become useless. Signed-off-by: Benoit Cousson <b-cousson@ti.com> Cc: Paul Walmsley <paul@pwsan.com> Cc: Rajendra Nayak <rnayak@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
2011-07-09OMAP4: clock data: Re-order some clock nodes and structure fieldsBenoit Cousson1-32/+34
A couple of fieds were edited manually and thus do not stick to the template used by the generator and by other structures. Move them to the correct location. Signed-off-by: Benoit Cousson <b-cousson@ti.com> Cc: Paul Walmsley <paul@pwsan.com> [paul@pwsan.com: dropped the UNIPRO changes since those will be removed in a later patch] Signed-off-by: Paul Walmsley <paul@pwsan.com>
2011-07-09OMAP4: clock data: Remove usb_host_fs clkdev with NULL devBenoit Cousson1-3/+0
usb_host_fs_fck does have a clkdev mapping with "usbhs-omap.0" and "fs_fck" alias used by the driver. The entry with NULL dev is thus not needed anymore. Signed-off-by: Benoit Cousson <b-cousson@ti.com> Cc: Paul Walmsley <paul@pwsan.com> Cc: Felipe Balbi <balbi@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
2011-07-09OMAP4: clock data: Add sddiv to USB DPLLBenoit Cousson1-0/+1
The USB DPLL is a J-Type DPLL with the sddiv extra parameter. Add it in USB DPLL. Signed-off-by: Benoit Cousson <b-cousson@ti.com> Cc: Paul Walmsley <paul@pwsan.com> [paul@pwsan.com: dropped UNIPRO change since it is removed in a later patch] Signed-off-by: Paul Walmsley <paul@pwsan.com>
2011-07-08OMAP4: clocks: Update the clock tree with 4460 clock nodesRajendra Nayak1-0/+39
Add the new clock nodes (bandgap_ts_fclk, div_ts_ck) for omap4460. Handle these nodes using the clock flags (CK_*). Signed-off-by: Rajendra Nayak <rnayak@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Benoit Cousson <b-cousson@ti.com> Reviewed-by: Kevin Hilman <khilman@ti.com> Acked-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2011-04-20OMAP4: clock data: Change DSS clock aliasesTomi Valkeinen1-7/+2
DSS driver has used fck and ick clocks on OMAP2/3 to get DSS HW up and running, and also to get the pixel clock's source clock rate from the fck. On OMAP4 the clock data is set up in a different way, as there's no ick, dss_fck points to a fake clock which just affects DSS's MODULEMODE, and dss_dss_clk if the DSS_FCK. >From DSS driver's point of view the dss_fck sounds like an ick, and dss_dss_clk is the fck. While this is not entirely correct from HW point of view, especially for the ick, configuring the clock aliases that way makes DSS "just work" with OMAP4's clock setup. In the (hopefully near) future DSS driver will be reworked to use pm_runtime support which should clean up the clock code. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> Cc: Benoît Cousson <b-cousson@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
2011-03-22Merge branch 'for-paul' of git://gitorious.org/linux-omap-dss2/linuxPaul Mundt1-5/+10
Conflicts: arch/arm/mach-omap2/board-overo.c Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2011-03-17Merge branch 'omap-for-linus' of ↵Linus Torvalds1-33/+44
git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6 * 'omap-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6: (258 commits) omap: zoom: host should not pull up wl1271's irq line arm: plat-omap: iommu: fix request_mem_region() error path OMAP2+: Common CPU DIE ID reading code reads wrong registers for OMAP4430 omap4: mux: Remove duplicate mux modes omap: iovmm: don't check 'da' to set IOVMF_DA_FIXED flag omap: iovmm: disallow mapping NULL address when IOVMF_DA_ANON is set omap2+: mux: Fix compile when CONFIG_OMAP_MUX is not selected omap4: board-omap4panda: Initialise the serial pads omap3: board-3430sdp: Initialise the serial pads omap4: board-4430sdp: Initialise the serial pads omap2+: mux: Add macro for configuring static with omap_hwmod_mux_init omap2+: mux: Remove the use of IDLE flag omap2+: Add separate list for dynamic pads to mux perf: add OMAP support for the new power events OMAP4: Add IVA OPP enteries. OMAP4: Update Voltage Rail Values for MPU, IVA and CORE OMAP4: Enable 800 MHz and 1 GHz MPU-OPP OMAP3+: OPP: Replace voltage values with Macros OMAP3: wdtimer: Fix CORE idle transition Watchdog: omap_wdt: add fine grain runtime-pm ... Fix up various conflicts in - arch/arm/mach-omap2/board-omap3evm.c - arch/arm/mach-omap2/clock3xxx_data.c - arch/arm/mach-omap2/usb-musb.c - arch/arm/plat-omap/include/plat/usb.h - drivers/usb/musb/musb_core.h
2011-03-11OMAP4: DSS2: clocks: Add ick as dummy clockSumit Semwal1-0/+5
DSS code uses ick as one of the clocks in clk_get/clk_put. OMAP4 clock database doesn't have ick for DSS, so adding ick as dummy clock. This is needed for backward compatibility with OMAP2/3. Once pm_runtime* APIs get introduced in DSS, this will be revisited. Signed-off-by: Sumit Semwal <sumit.semwal@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-03-11OMAP2PLUS: clocks: Align DSS clock names and rolesSumit Semwal1-5/+5
Currently, clock database has <dev, clock-name> tuples for DSS2. Because of this, the clock names are different across different OMAP platforms. This patch aligns the DSS2 clock names and roles across OMAP 2420, 2430, 3xxx, 44xx platforms in the clock databases, hwmod databases for opt-clocks, and DSS clock handling. This ensures that clk_get/put/enable/disable APIs in DSS can use uniform role names. Signed-off-by: Sumit Semwal <sumit.semwal@ti.com> Acked-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-03-10Merge remote branches 'remotes/origin/pwrdm_clkdm_b_2.6.39', ↵Paul Walmsley1-33/+44
'remotes/origin/pwrdm_add_can_lose_context_fns_2.6.39', 'remotes/origin/omap_device_a_2.6.39', 'remotes/origin/mmc_a_2.6.39', 'remotes/origin/hwmod_b_2.6.39', 'remotes/origin/dmtimer_a_2.6.39', 'remotes/origin/pwrdm_clkdm_a_2.6.39', 'remotes/origin/clkdm_statdep_omap4_2.6.39', 'remotes/origin/clk_a_2.6.39', 'remotes/origin/clk_autoidle_a_2.6.39', 'remotes/origin/clk_autoidle_b_2.6.39', 'remotes/origin/clk_b_2.6.39', 'remotes/origin/clk_clkdm_a_2.6.39', 'remotes/origin/misc_a_2.6.39', 'remotes/origin/for_2.6.39/omap3_hwmod_data' and 'remotes/origin/wdtimer_a_2.6.39' into tmp-integration-2.6.39-20110310-024
2011-03-01OMAP: hsmmc: Rename the device and driverKishore Kadiyala1-10/+10
Modifying the device & driver name from "mmci-omap-hs" to "omap_hsmmc". Signed-off-by: Kishore Kadiyala <kishore.kadiyala@ti.com> Acked-by: Benoit Cousson<b-cousson@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2011-03-01arm: omap: usb: clock entries for omap3 and omap4Keshava Munegowda1-5/+5
The devices of clocks are set to usbhs, so that only usbhs common driver can invoke these clocks. The dummy per port clocks are added to omap3 clock data base. This helps to invoke common clock get APIs for omap3 and omap4. Signed-off-by: Keshava Munegowda <keshava_mgowda@ti.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
2011-02-25OMAP2+: clock: disable autoidle on all clocks during clock initPaul Walmsley1-0/+3
Disable autoidle on all clocks during clock framework initialization. (If CONFIG_PM is set, autoidle is re-enabled for all clocks later in the boot process.) The principle behind this patch, and some similar patches, is that the kernel should start with all power management features disabled. Later in the boot process, the PM code, if compiled in with CONFIG_PM, enables or re-enables power management features. Signed-off-by: Paul Walmsley <paul@pwsan.com> Tested-by: Rajendra Nayak <rnayak@ti.com> Reviewed-by: Kevin Hilman <khilman@ti.com>
2011-02-25omap4: dpll: Enable auto gate control for all MX postdividersRajendra Nayak1-22/+30
Enable hardware gate control for all dpll MX and X2 postdividers. This requires the allow_idle/deny_idle functions to be populated for all clock nodes (mx/x2 post dividers) in clkops. Signed-off-by: Rajendra Nayak <rnayak@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
2011-02-25OMAP3/4: DPLL: Add allow_idle/deny_idle support for all DPLL'sRajendra Nayak1-1/+1
All OMAP3/4 dpll's support hardware level autogating. Populate allow_idle/deny_idle function pointers for all DPLL's in clkops. Signed-off-by: Rajendra Nayak <rnayak@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
2011-01-18OMAP: PRCM: remove duplicated headersFelipe Balbi1-1/+0
A few headers are included twice, remove them. Found the following errors using make includecheck: arch/arm/mach-omap2/clock44xx_data.c: prm44xx.h is included more than once. arch/arm/mach-omap2/clockdomains44xx_data.c: cm1_44xx.h is included more than once. arch/arm/mach-omap2/clockdomains44xx_data.c: cm2_44xx.h is included more than once. arch/arm/mach-omap2/powerdomain2xxx_3xxx.c: prm-regbits-34xx.h is included more than once. Cc: Paul Walmsley <paul@pwsan.com> Cc: Tony Lindgren <tony@atomide.com> Cc: Russell King <linux@arm.linux.org.uk> Signed-off-by: Felipe Balbi <balbi@ti.com> [paul@pwsan.com: dropped lists from patch cc:s; tweaked subject line] Signed-off-by: Paul Walmsley <paul@pwsan.com>
2011-01-07Merge branch 'usb-next' of ↵Linus Torvalds1-1/+6
git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb-2.6 * 'usb-next' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb-2.6: (144 commits) USB: add support for Dream Cheeky DL100B Webmail Notifier (1d34:0004) USB: serial: ftdi_sio: add support for TIOCSERGETLSR USB: ehci-mxc: Setup portsc register prior to accessing OTG viewport USB: atmel_usba_udc: fix freeing irq in usba_udc_remove() usb: ehci-omap: fix tll channel enable mask usb: ohci-omap3: fix trivial typo USB: gadget: ci13xxx: don't assume that PAGE_SIZE is 4096 USB: gadget: ci13xxx: fix complete() callback for no_interrupt rq's USB: gadget: update ci13xxx to work with g_ether USB: gadgets: ci13xxx: fix probing of compiled-in gadget drivers Revert "USB: musb: pm: don't rely fully on clock support" Revert "USB: musb: blackfin: pm: make it work" USB: uas: Use GFP_NOIO instead of GFP_KERNEL in I/O submission path USB: uas: Ensure we only bind to a UAS interface USB: uas: Rename sense pipe and sense urb to status pipe and status urb USB: uas: Use kzalloc instead of kmalloc USB: uas: Fix up the Sense IU usb: musb: core: kill unneeded #include's DA8xx: assign name to MUSB IRQ resource usb: gadget: g_ncm added ... Manually fix up trivial conflicts in USB Kconfig changes in: arch/arm/mach-omap2/Kconfig arch/sh/Kconfig drivers/usb/Kconfig drivers/usb/host/ehci-hcd.c and annoying chip clock data conflicts in: arch/arm/mach-omap2/clock3xxx_data.c arch/arm/mach-omap2/clock44xx_data.c
2010-12-22OMAP4: clock data: Add missing fixed divisorsJon Hunter1-11/+22
The following OMAP4 clocks have the following fixed divisors that determine the frequency at which these clocks operate. These dividers are defined by the PRCM specification and without these dividers the rates of the below clocks are calculated incorrectly. This may cause internal peripherals using these clocks to operate at the wrong frequency. - abe_24m_fclk (freq = divided-by-8) - ddrphy_ck (freq = parent divided-by-2) - dll_clk_div_ck (freq = parent divided-by-2) - per_hs_clk_div_ck (freq = parent divided-by-2) - usb_hs_clk_div_ck (freq = parent divided-by-3) - func_12m_fclk (freq = parent divided-by-16) - func_24m_clk (freq = parent divided-by-4) - func_24mc_fclk (freq = parent divided-by-8) - func_48mc_fclk (freq = divided-by-4) - lp_clk_div_ck (freq = divided-by-16) - per_abe_24m_fclk (freq = divided-by-4) Signed-off-by: Jon Hunter <jon-hunter@ti.com> Signed-off-by: Benoit Cousson <b-cousson@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Kevin Hilman <khilman@deeprootsystems.com> Cc: Rajendra Nayak <rnayak@ti.com>
2010-12-21OMAP4: clock data: Keep L3INSTR clock domain modulemode under HW controlSantosh Shilimkar1-0/+3
L3INSTR clock domain is read only register and its reset value is HW_AUTO. The modules withing this clock domain needs to be kept under hardware control. MODULEMODE: - 0x0: Module is disable by software. Any INTRCONN access to module results in an error, except if resulting from a module wakeup (asynchronous wakeup). - 0x1: Module is managed automatically by hardware according to clock domain transition. A clock domain sleep transition put module into idle. A wakeup domain transition put it back into function. If CLKTRCTRL=3, any INTRCONN access to module is always granted. Module clocks may be gated according to the clock domain state. This patch keeps CM_L3INSTR_L3_3_CLKCTRL, CM_L3INSTR_L3_INSTR_CLKCTRL and CM_L3INSTR_INTRCONN_WP1_CLKCTRL module mode under hardware control by using ENABLE_ON_INIT flag. Without this the OMAP4 device OFF mode SAR restore phase aborts during interconnect register restore phase. This can be also handled by doing explicit a clock enable and disable in the low power code since there is no direct module associated with it. But that seems not necessary since the clock domain is under HW control. Signed-off-by: Rajendra Nayak <rnayak@ti.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Benoit Cousson <b-cousson@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
2010-12-21OMAP4: clocks: add dummy clock for mailboxHari Kanigeri1-0/+1
In omap4, there is no explicit configuration register to enable mailbox clocks. Defining dummy clock for mailbox clock module to keep the mailbox driver backward compatible with previous omaps. Signed-off-by: Hari Kanigeri <h-kanigeri2@ti.com> Acked-by: Benoît Cousson <b-cousson@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
2010-12-21OMAP: clock: fix configuration of J-Type DPLLs to work for OMAP3 and OMAP4Jon Hunter1-1/+2
J-Type DPLLs have additional configuration parameters that need to be programmed when setting the multipler and divider for the DPLL. These parameters being the sigma delta divider (SD_DIV) for the DPLL and the digital controlled oscillator (DCO) to be used by the DPLL. The current code is implemented specifically to configure the OMAP3630 PER J-Type DPLL. The OMAP4430 USB DPLL is also a J-Type DPLL and so this code needs to be updated to work for both OMAP3 and OMAP4 devices and any other future devices that have J-TYPE DPLLs. For the OMAP3630 PER DPLL both the SD_DIV and DCO paramenters are used but for the OMAP4430 USB DPLL only the SD_DIV field is used. The current implementation will only program the SD_DIV and DCO fields if the DPLL has both and hence this does not work for OMAP4430. In order to make the code more generic add two new fields to the dpll_data structure for the SD_DIV field and DCO field bit-masks and only program these fields if the masks are defined for a specific DPLL. This simplifies the code and allows us to remove the flag DPLL_NO_DCO_SEL. Tested on OMAP36xx Zoom3 and OMAP4 Blaze. Signed-off-by: Jon Hunter <jon-hunter@ti.com> [paul@pwsan.com: removed explicit inlining and added '_' prefix on lookup_*() functions; added testing info to commit message; added 35xx comments back in] Signed-off-by: Paul Walmsley <paul@pwsan.com>
2010-12-21OMAP4: hwmod & clock data: Fix GPIO opt_clks and ocp_if iclkBenoit Cousson1-6/+6
Fix opt clocks name in clock framework and hwmod. Add the missing iclk in the ocp_if structure. Add the HWMOD_CONTROL_OPT_CLKS_IN_RESET flag to ensure the the GPIO optional clock is enable during reset. Signed-off-by: Benoit Cousson <b-cousson@ti.com> Tested-by: Charulatha V <charu@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Rajendra Nayak <rnayak@ti.com>
2010-12-21OMAP4: clock data: Export control to enable/disable CORE/PER M3 clocksRajendra Nayak1-2/+6
The CORE and PER M3 post dividers are different from the rest of the DPLL post dividers as in they go to SCRM, and are used there to export clocks for instance used by external sensor. There is no automatic HW dependency in PRCM to manage them. Hence these two clocks (dpll post dividers) should be managed by SW and explicitly enabled/disabled. Add control in clock framework to handle that. Signed-off-by: Rajendra Nayak <rnayak@ti.com> Signed-off-by: Benoit Cousson <b-cousson@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
2010-12-21OMAP4: clock data: Add SCRM auxiliary clock nodesRajendra Nayak1-0/+175
Add support for auxiliary clocks nodes which are part of SCRM. Signed-off-by: Rajendra Nayak <rnayak@ti.com> Signed-off-by: Benoit Cousson <b-cousson@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
2010-12-21OMAP4: clock data: Add missing fields in iva_hsd_byp_clk_mux_ckJonathan Bergsagel1-1/+5
Add register address, mask and link to the clksel structure that were missing in the IVA DPLL mux clock node. Signed-off-by: Jonathan Bergsagel <jbergsagel@ti.com> Signed-off-by: Benoit Cousson <b-cousson@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Rajendra Nayak <rnayak@ti.com>
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