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2022-10-17ARM: dts: DBx500 cryp and hash uses power domainLinus Walleij1-4/+2
The cryp and hash blocks of the DBx500 uses the VAPE power domain, the special regulator is a leftover that is not used anymore. Link: https://lore.kernel.org/r/20220721153610.1053845-1-linus.walleij@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-07-05ARM: dts: ux500: Drop unused i2c power domain supplyLinus Walleij1-5/+0
This regulator supply is replaced by the proper power domain. Reported-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220701225339.814962-1-linus.walleij@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-04-04ARM: dts: ste-dbx: Update spi clock-names propertyKuldeep Singh1-6/+6
Now that spi pl022 binding only accept "sspclk" as clock name, ST ericsson platform with "SSPCLK" clock name start raising dtbs_check warnings. Make necessary changes to update this property in order to make it compliant with binding. clock-names:0: 'sspclk' was expected Signed-off-by: Kuldeep Singh <singh.kuldeep87k@gmail.com> Link: https://lore.kernel.org/r/20220312113853.63446-5-singh.kuldeep87k@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-11-23ARM: dts: ux500: Add reset lines to IP blocksLinus Walleij1-0/+26
The new reset controller makes is possible to add reset lines to a host of IP blocks in the DB8500/U8500. Cc: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-01-22ARM: dts: Fix up MMC host node namesLinus Walleij1-6/+6
The standard mandates that these nodes be named mmc@... not sdi_foo@... Acked-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2020-11-06ARM: dts: ux500: Rename DSI controller nodesLinus Walleij1-3/+3
Rename the DSI controller nodes from "dsi-controller@" to "dsi@" so they match the naming convention in the YAML schema for DSI controllers. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20201104133758.1373298-1-linus.walleij@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2020-07-07ARM: dts: ste: Align L2 cache-controller nodename with dtschemaKrzysztof Kozlowski1-1/+1
Fix dtschema validator warnings like: l2-cache: $nodename:0: 'l2-cache' does not match '^(cache-controller|cpu)(@[0-9a-f,]+)*$' Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Link: https://lore.kernel.org/r/20200626080552.3627-1-krzk@kernel.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2020-02-10ARM: dts: ux500: Fix up DSI controller nodesLinus Walleij1-3/+3
These nodes should be named dsi-controller@* so fix it up. Cc: Stephan Gerhold <stephan@gerhold.net> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-12-09ARM: dts: ux500: Break out DB8500 DTSILinus Walleij1-5/+0
The DB8500 exists in an enhanced variant named DB8520 for some machines. To clearly distinguish between the different machines, create an explicit db8500.dtsi and move the operating points (only known difference so far) to that file, so we can add an explicit db8520.dtsi after this. Cc: Stephan Gerhold <stephan@gerhold.net> Link: https://lore.kernel.org/r/20191126124738.77690-1-linus.walleij@linaro.org Reviewed-by: Stephan Gerhold <stephan@gerhold.net> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-12-09ARM: dts: ux500: Use "arm,pl031" compatible for PL031Stephan Gerhold1-1/+1
The Ux500 device tree uses "arm,rtc-pl031" as compatible for PL031. All other boards in Linux describe it using "arm,pl031" instead. This works because the compatible is not actually used in Linux: AMBA devices get probed based on "arm,primecell" and their peripheral ID. Nevertheless, some other projects (e.g. U-Boot) rely on the compatible to probe the device with the correct driver. Those will look for "arm,pl031" instead of "arm,rtc-pl031", preventing the RTC from being probed. Change it to "arm,pl031" to match all other boards. Signed-off-by: Stephan Gerhold <stephan@gerhold.net> Link: https://lore.kernel.org/r/20191124205110.48031-1-stephan@gerhold.net Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-12-09ARM: dts: ux500: Add "simple-bus" compatible to soc nodeStephan Gerhold1-1/+1
The "soc" node in the Ux500 device tree does not need any special handling - it is just a simple I/O bus that can be accessed without additional configuration. Therefore we can additionally describe it as compatible with "simple-bus". This can be used by platforms to probe devices under the soc node without special handling for our custom "stericsson,db8500" compatible (e.g. in U-Boot). Signed-off-by: Stephan Gerhold <stephan@gerhold.net> Link: https://lore.kernel.org/r/20191124195728.32226-1-stephan@gerhold.net Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-12-09ARM: dts: ux500: Remove ux500_ prefix from ux500_serial* labelsStephan Gerhold1-6/+6
ux500_serial{0,1,2} are the only labels with ux500_ prefix in ste-dbx5x0.dtsi, the other labels (gpio0, msp, ...) do not use any prefix. Remove it for consistency. Signed-off-by: Stephan Gerhold <stephan@gerhold.net> Link: https://lore.kernel.org/r/20191125170428.76069-4-stephan@gerhold.net Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-12-09ARM: dts: ux500: Move serial aliases to ste-dbx5x0.dtsiStephan Gerhold1-0/+3
Now that we have aliases for I2C and SPI in ste-dbx5x0.dtsi, it does not make much sense to keep only the aliases for UART separately in each board device tree. Considering that all boards set the same aliases for the serial ports there is no reason to keep them separated either. Move them to ste-dbx5x0.dtsi and remove the aliases from the board-specific device tree parts. Signed-off-by: Stephan Gerhold <stephan@gerhold.net> Link: https://lore.kernel.org/r/20191125170428.76069-3-stephan@gerhold.net Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-12-09ARM: dts: ux500: Add aliases for I2C and SPI busesStephan Gerhold1-11/+24
Now that we disable the I2C/SPI buses by default, is is even more important to assign aliases to the I2C/SPI device nodes. Otherwise, enabling/disabling one of them will potentially change all device IDs, e.g. i2c2 will be named i2c-0 if it is the only enabled I2C bus. Add aliases for the I2C and SPI buses to avoid this. Signed-off-by: Stephan Gerhold <stephan@gerhold.net> Link: https://lore.kernel.org/r/20191125170428.76069-2-stephan@gerhold.net Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-12-09ARM: dts: ux500: Disable I2C/SPI buses by defaultStephan Gerhold1-0/+22
At the moment, all 5 I2C and 6 SPI buses are probed and exposed to user-space by default - even if they are not muxed to any pins on the board. This means that user-space sees an I2C/SPI bus that cannot be actually used properly. In some cases this was used to put the corresponding pins into a low power sleep mode - but even then the pins first need to be configured by the board-specific device tree part. Avoid exposing unconfigured devices to user-space by disabling the I2C/SPI buses by default. Enable them in the board device trees when needed. Signed-off-by: Stephan Gerhold <stephan@gerhold.net> Link: https://lore.kernel.org/r/20191125170428.76069-1-stephan@gerhold.net Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-10-01ARM: dts: ux500: Fix up the CPU thermal zoneLinus Walleij1-3/+8
This fixes up the default ux500 CPU thermal zone: - Set polling delay to 0 and explain why - Set passive polling delay to 250 - Remove restrictions from the CPU cooling device, we should use all cpufreq steps to cool down if needed. Link: https://lore.kernel.org/r/20191001074628.8122-1-linus.walleij@linaro.org Fixes: b786a05f6ce4 ("ARM: dts: ux500: Update thermal zone") Suggested-by: Daniel Lezcano <daniel.lezcano@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Daniel Lezcano <daniel.lezcano@linaro.org> Signed-off-by: Olof Johansson <olof@lixom.net>
2019-08-28ARM: dts: ux500: Update thermal zoneLinus Walleij1-21/+36
After moving the DB8500 thermal driver to use device tree we define the default thermal zone for the Ux500 in the device tree replacing the oldstyle hardcoded trigger points. This default thermal zone utilizes the cpufreq driver (using the generic OF cpufreq back-end) as a passive cooling device, and defines a critical trip point when the temperature goes above 85 degrees celsius which will (hopefully) make the system shut down if the temperature cannot be controlled. This default policy can later be augmented for specific subdevices if these have tighter temperature conditions. After this patch we get: /sys/class/thermal/thermal_zone0 (CPU thermal zone) This reports the rough temperature and trip points from the thermal zone in the device tree. By executing two yes > /dev/null & jobs fully utilizing the two CPU cores we can notice the temperature climbing in the thermal zone in response and falling when we kill the jobs. /syc/class/thermal/cooling_device0 (cpufreq cooling) this reports all 4 available cpufreq frequencies as states. Suggested-by: Daniel Lezcano <daniel.lezcano@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-08-22ARM: dts: ux500: Move ab8500 nodes to ste-ab8500.dtsiStephan Gerhold1-208/+0
Some Ux500 devices use the newer AB8505 PMIC instead of AB8500. Although they are very similar, there are subtle differences like the number of regulators or the available GPIO pins. At the moment, ste-dbx5x0.dtsi always configures the AB8500 PMIC. To support devices with AB8505, it is necessary to split the AB8500-specific parts into a separate .dtsi file. Boards can then select the PMIC by including either ste-ab8500.dtsi or ste-ab8505.dtsi. Signed-off-by: Stephan Gerhold <stephan@gerhold.net> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-23ARM: dts: ux500: Fix up the thermal nodesLinus Walleij1-1/+21
The thermal driver for the DB8500 was never properly converted to device tree, the node should definitely be activated for all board variants so move this down into the main SoC DTSI, and default on. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-23ARM: dts: ste: Update coresight DT bindingsLeo Yan1-2/+2
CoreSight DT bindings have been updated, thus the old compatible strings are obsolete and the drivers will report warning if DTS uses these obsolete strings. This patch switches to the new bindings for CoreSight dynamic funnel and static replicator, so can dismiss warning during initialisation. Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Lee Jones <lee.jones@linaro.org> Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Cc: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Leo Yan <leo.yan@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-05-30treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 159Thomas Gleixner1-7/+1
Based on 1 normalized pattern(s): the code contained herein is licensed under the gnu general public license you may obtain a copy of the gnu general public license version 2 or later at the following locations http www opensource org licenses gpl license html http www gnu org copyleft gpl html extracted by the scancode license scanner the SPDX license identifier GPL-2.0-or-later has been chosen to replace the boilerplate/reference in 161 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Richard Fontana <rfontana@redhat.com> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190527070033.383790741@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-04-17ARM: dts: Ux500: Add MCDE and Samsung displayLinus Walleij1-11/+39
This adds and updates the device tree nodes for the MCDE display controller and connects the Samsung display to the TVK1281618 user interface board (UIB) so we get nicely working graphics on this reference design. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-04-17ARM: dts: ux500: Add Mali-400Linus Walleij1-0/+24
This adds the Mali-400 block, also known as SGA500 or the Smart Graphics Adapter, to the DBx500 DTS file. All resources and bindings are already in place so this just works. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-09-20ARM: dts: ux500: Mark PRCMU as syscon compatibleLinus Walleij1-1/+1
We need to distribute out the responsibilities of the PRCMU registers instead of having one big lump handling everything. By making it syscon compatible, we can start grabbing the register map elsewhere when needed. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-09-20arm: dts: ste: Update coresight bindings for hardware portSuzuki K Poulose1-32/+33
Switch to the new coresight bindings Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-09-20ARM: dts: ste: Fix SPI controller node namesRob Herring1-2/+2
SPI controller nodes should be named 'spi' rather than 'ssp'. Fixing the name enables dtc SPI bus checks. Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-09-20ARM: dts: ux500: Get rid of DTC warningsLinus Walleij1-1/+6
By removing the reference to skeleton.dtsi, defining chosen {} and proper memory nodes we get warning-free device trees for the Ux500. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-09-20ARM: dts: ux500: Correct SCU unit addressGeert Uytterhoeven1-1/+1
The unit address of the Cortex-A9 SCU device node contains one zero too many. Remove it. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-08-22ARM: dts: augment Ux500 to use DT cpufreqLinus Walleij1-7/+8
This adds the operating points to the Ux500 device tree and deletes the old special-purpose cpufreq node, as we can now use the generic DT cpufreq driver. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2017-04-15Merge back cpufreq core changes for v4.12.Rafael J. Wysocki1-5/+0
2017-03-16cpufreq: dbx500: Manage cooling device from cpufreq driverViresh Kumar1-5/+0
The best place to register the CPU cooling device is from the cpufreq driver as we would know if all the resources are already available or not. That's what is done for the cpufreq-dt.c driver as well. The cpu-cooling driver for dbx500 platform was just (un)registering with the thermal framework and that can be handled easily by the cpufreq driver as well and in proper sequence as well. Get rid of the cooling driver and its its users and manage everything from the cpufreq driver instead. Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Tested-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2017-03-13ARM: dts: add the AB8500 clocks to the device treeLinus Walleij1-0/+19
This adds the AB8500 clocks to the device tree using the new bindings from the clk subsystem, making audio work again. Cc: Lee Jones <lee.jones@linaro.org> Cc: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Olof Johansson <olof@lixom.net>
2017-01-31ARM: dts: add the AB8500 sysclk to the device treesLinus Walleij1-0/+2
This clock has been missing since some early stages of device tree conversion. Adding the right clocks to the device tree makes USB work again. Cc: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-06-08ARM: dts: Ux500: move compatible string to chipsetLinus Walleij1-0/+1
Move the compatible string "stericsson,ab8500" from the board definitions into the main node in the chipset file where it belongs. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-03-29ARM: dts: ux500: use the GIC include headerLinus Walleij1-45/+46
Use the <dt-bindings/interrupt-controller/arm-gic.h> header for generating the flags for the first cell of the interrupt definitions. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-03-29ARM: dts: ux500: use the GPIO DT headerLinus Walleij1-0/+1
Use the <dt-bindings/gpio/gpio.h> header instead of using hardcoded values for the GPIO flags. Eradicate the totally bogus "0x4" flag used and set that to GPIO_ACTIVE_HIGH as is proper, switch the inverted card detect on the Snowball to flag using GPIO_ACTIVE_LOW instead of using the MMC-specific inversion flag. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-11-17ARM: ux500: remove regulator-compatible usageJavier Martinez Canillas1-33/+0
The regulator-compatible property from the regulator DT binding was deprecated and the correct approach is to use the node's name. This patch has no functional changes since the values of the node's name and the regulator-compatible match for all the regulators. Signed-off-by: Javier Martinez Canillas <javier@osg.samsung.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-09-04Merge tag 'pinctrl-v4.3-1' of ↵Linus Torvalds1-10/+13
git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull pin control updates from Linus Walleij: "This is the bulk of pin control changes for the v4.3 development cycle. Like with GPIO it's a lot of stuff. If my subsystems are any sign of the overall tempo of the kernel v4.3 will be a gigantic diff. [ It looks like 4.3 is calmer than 4.2 in most other subsystems, but we'll see - Linus ] Core changes: - It is possible configure groups in debugfs. - Consolidation of chained IRQ handler install/remove replacing all call sites where irq_set_handler_data() and irq_set_chained_handler() were done in succession with a combined call to irq_set_chained_handler_and_data(). This series was created by Thomas Gleixner after the problem was observed by Russell King. - Tglx also made another series of patches switching __irq_set_handler_locked() for irq_set_handler_locked() which is way cleaner. - Tglx also wrote a good bunch of patches to make use of irq_desc_get_xxx() accessors and avoid looking up irq_descs from IRQ numbers. The goal is to get rid of the irq number from the handlers in the IRQ flow which is nice. Driver feature enhancements: - Power management support for the SiRF SoC Atlas 7. - Power down support for the Qualcomm driver. - Intel Cherryview and Baytrail: switch drivers to use raw spinlocks in IRQ handlers to play nice with the realtime patch set. - Rework and new modes handling for Qualcomm SPMI-MPP. - Pinconf power source config for SH PFC. New drivers and subdrivers: - A new driver for Conexant Digicolor CX92755. - A new driver for UniPhier PH1-LD4, PH1-Pro4, PH1-sLD8, PH1-Pro5, ProXtream2 and PH1-LD6b SoC pin control support. - Reverse-egineered the S/PDIF settings for the Allwinner sun4i driver. - Support for Qualcomm Technologies QDF2xxx ARM64 SoCs - A new Freescale i.mx6ul subdriver. Cleanup: - Remove platform data support in a number of SH PFC subdrivers" * tag 'pinctrl-v4.3-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (95 commits) pinctrl: at91: fix null pointer dereference pinctrl: mediatek: Implement wake handler and suspend resume pinctrl: mediatek: Fix multiple registration issue. pinctrl: sh-pfc: r8a7794: add USB pin groups pinctrl: at91: Use generic irq_{request,release}_resources() pinctrl: cherryview: Use raw_spinlock for locking pinctrl: baytrail: Use raw_spinlock for locking pinctrl: imx6ul: Remove .owner field pinctrl: zynq: Fix typos in smc0_nand_grp and smc0_nor_grp pinctrl: sh-pfc: Implement pinconf power-source param for voltage switching clk: rockchip: add pclk_pd_pmu to the list of rk3288 critical clocks pinctrl: sun4i: add spdif to pin description. pinctrl: atlas7: clear ugly branch statements for pull and drivestrength pinctrl: baytrail: Serialize all register access pinctrl: baytrail: Drop FSF mailing address pinctrl: rockchip: only enable gpio clock when it setting pinctrl/mediatek: fix spelling mistake in dev_err error message pinctrl: cherryview: Serialize all register access pinctrl: UniPhier: PH1-Pro5: add I2C ch6 pin-mux setting pinctrl: nomadik: reflect current input value ...
2015-08-31Merge tag 'clk-for-linus-4.3' of ↵Linus Torvalds1-0/+7
git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk updates from Michael Turquette: "The clk framework changes for 4.3 are mostly updates to existing drivers and the addition of new clock drivers. Stephen Boyd has also done a lot of subsystem-wide driver clean-ups (thanks!). There are also fixes to the framework core and changes to better split clock provider drivers from clock consumer drivers" * tag 'clk-for-linus-4.3' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (227 commits) clk: s5pv210: add missing call to samsung_clk_of_add_provider() clk: pistachio: correct critical clock list clk: pistachio: Fix PLL rate calculation in integer mode clk: pistachio: Fix override of clk-pll settings from boot loader clk: pistachio: Fix 32bit integer overflows clk: tegra: Fix some static checker problems clk: qcom: Fix MSM8916 prng clock enable bit clk: Add missing header for 'bool' definition to clk-conf.h drivers/clk: appropriate __init annotation for const data clk: rockchip: register pll mux before pll itself clk: add bindings for the Ux500 clocks clk/ARM: move Ux500 PRCC bases to the device tree clk: remove duplicated code with __clk_set_parent_after clk: Convert __clk_get_name(hw->clk) to clk_hw_get_name(hw) clk: Constify clk_hw argument to provider APIs clk: Hi6220: add stub clock driver dt-bindings: clk: Hi6220: Document stub clock driver dt-bindings: arm: Hi6220: add doc for SRAM controller clk: atlas7: fix pll missed divide NR in fraction mode clk: atlas7: fix bit field and its root clk for coresight_tpiu ...
2015-08-24clk/ARM: move Ux500 PRCC bases to the device treeLinus Walleij1-0/+7
The base addresses for the Ux500 PRCC controllers are hardcoded, let's move them to the clock node in the device tree and delete the constants. Cc: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Olof Johansson <olof@lixom.net> Acked-by: Michael Turquette <mturquette@baylibre.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-08-06ARM: ux500: add an SMP enablement type and move cpu nodesLinus Walleij1-26/+27
The "cpus" node cannot be inside the "soc" node, while this works for the CoreSight blocks, the early boot code will look for "cpus" directly under the root node, so this is a hard convention. So move the CPU nodes. Augment the "reg" property to match what is actually in the hardware: 0x300 and 0x301 respectively. Then add an SMP enablement type to be used by the SMP init code, "ste,dbx500-smp". Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Olof Johansson <olof@lixom.net>
2015-07-27pinctrl/ARM: move GPIO and pinctrl deps to device treeLinus Walleij1-10/+13
This gets the GPIO ranges out of the driver and into the device tree where they belong. Standard DT bindings already exist for this. Since no systems with this are deployed we can just augment all device trees and the drivers at the same time and simplify the world. This also defines the array of GPIO chips related to the pin controller. Cc: arm@kernel.org Acked-by: Olof Johansson <olof@lixom.net> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-07-14ARM: ux500: define serial port aliasesLinus Walleij1-3/+3
This enumerates the PL011 serial ports on the Ux500. This is necessary to do if we want to remove one of the serial ports, since userspace depends on console to be present on ttyAMA2 and we must not break userspace. Cc: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Olof Johansson <olof@lixom.net>
2015-05-18ARM: ux500: define the backupram in the device treeLinus Walleij1-0/+9
The Ux500 SOCs have a special backup RAM that needs to be defined in the device tree. Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-05-15ARM: ux500: add SCU and WD to device treeLinus Walleij1-0/+12
The Ux500 like other Cortex-A9 SoC's has a Snoop Control Unit (SCU) and a Watchdog in the same address range as the local timers. Add these to the SoC device tree. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2015-05-13Merge tag 'ux500-v4.2-dt' of ↵Arnd Bergmann1-0/+154
git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson into next/dt Merge "Ux500 Device Tree changes for the v4.2 series" form Linus Walleij: Define CPU topology, connect that with CoreSight blocks, add sensor information to DT boards. * tag 'ux500-v4.2-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson: ARM: ux500: add the sensors to the STUIB board ARM: ux500: assign the sensor trigger IRQs ARM: ux500: fix lsm303dlh magnetometer compat string ARM: ux500: add CoreSight blocks to DTS file ARM: ux500: define CPU topology
2015-05-13ARM: ux500: add CoreSight blocks to DTS fileLinus Walleij1-0/+128
This registers all the CoreSight blocks on the DB8500 SoC: each core has a PTM (v1.0, r1p0-00rel0) connected, both connected to a funnel (DK-TM908-r0p1-00rel0) which in turn connects to a replicator (DM-TM909-r0p1-00rel0). The replicator has two outputs, port 0 to a TPIU interface and port 1 to an ETB (DK-TM907-r0p3-00rel0). The CoreSight blocks are all clocked by the APEATCLK from the PRCMU and their AHB interconnect is clocked from a separate clock called APETRACECLK. The SoC also has a CTI/CTM block which can be added later as we have upstream support in the CoreSight subsystem. Acked-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-04-27ARM: ux500: define CPU topologyLinus Walleij1-0/+26
The CPU topology is unspecified for Ux500 but will be needed for things like CoreSight. Let's just add it. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-04-27ARM: ux500: Move GPIO regulator for SD-card into board DTSsUlf Hansson1-17/+0
The GPIO regulator for the SD-card isn't a ux500 SOC configuration, but instead it's specific to the board. Move the definition of it, into the board DTSs. Fixes: c94a4ab7af3f ("ARM: ux500: Disable the MMCI gpio-regulator by default") Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-10-28ARM: ux500: Add i2c devices to the VAPE PM domainUlf Hansson1-0/+5
The i2c-nomadik driver handle these devices properly from a runtime PM perspective. Therefore, let's add them into VAPE PM domain for ux500. Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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