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2015-06-30ARM: mvebu: update Ethernet compatible string for Armada XPSimon Guinot1-1/+1
This patch updates the Ethernet DT nodes for Armada XP SoCs with the compatible string "marvell,armada-xp-neta". Signed-off-by: Simon Guinot <simon.guinot@sequanux.org> Fixes: 77916519cba3 ("arm: mvebu: Armada XP MV78230 has only three Ethernet interfaces") Cc: <stable@vger.kernel.org> # v3.8+ Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2015-03-04ARM: mvebu: remove aliases for Ethernet devices on Armada 370/375/38x/XPThomas Petazzoni1-1/+0
Having aliases for Ethernet devices is useless, since the networking subsystem unfortunately doesn't care about aliases to name network interfaces. Note that the 'aliases' nodes in armada-370-xp.dtsi and armada-xp.dtsi become empty, but that we keep it as is since a followup patch will re-add some aliases to it. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2015-01-26ARM: mvebu: armada-xp-mv78260: Relicense the device tree under GPLv2+/X11Gregory CLEMENT1-3/+37
The current GPL only licensing on the device tree makes it very impractical for other software components licensed under another license. In order to make it easier for them to reuse our device trees, relicense our device trees under a GPL/X11 dual-license. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Acked-by: Jason Cooper <jason@lakedaemon.net> Acked-by: Arnaud Ebalard <arno@natisbad.org> Acked-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: Willy Tarreau <w@1wt.eu>
2014-11-02ARM: mvebu: armada-xp: Use pinctrl node aliasSebastian Hesselbarth1-4/+4
Armada XP pinctrl node gained an alias, make use of it. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Tested-By: Benoit Masson <yahoo@perenite.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-11-02ARM: mvebu: armada-xp: Add node alias to pinctrl and add base addressSebastian Hesselbarth1-1/+1
In other MVEBU SoCs, the pin controller node is called pin-ctrl with its base address added. Also, we have a node alias to access the pinctrl node easily. Fix this for Armada XP pinctrl nodes to be consistent with other SoCs. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Tested-By: Benoit Masson <yahoo@perenite.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-11-02ARM: mvebu: armada-xp: Consolidate pinctrl nodeSebastian Hesselbarth1-7/+0
All current Armada XP SoCs have their pin controller at 0x18000/0x38. Move the common properties of pinctrl nodes to armada-xp.dtsi to allow to share pinctrl settings later. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Tested-By: Benoit Masson <yahoo@perenite.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-07-16ARM: mvebu: update Armada XP DT for dynamic frequency scalingThomas Petazzoni1-0/+2
In order to support dynamic frequency scaling: * the cpuclk Device Tree node needs to be updated to describe a second set of registers describing the PMU DFS registers. * the clock-latency property of the CPUs must be filled, otherwise the ondemand and conservative cpufreq governors refuse to work. The latency is high because the cost of a frequency transition is quite high on those CPUs. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Link: https://lkml.kernel.org/r/1404920715-19834-5-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-04-24ARM: mvebu: add enable-method property for CPUsThomas Petazzoni1-0/+1
This commit updates the Armada XP Device Trees (for the three variants of Armada XP) to declare the "enable-method" property for the CPUs, which helps operating systems find the appropriate logic to manage the CPUs, especially to boot secondary CPUs. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Link: https://lkml.kernel.org/r/1397483648-26611-4-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-02-05ARM: mvebu: dt: add missing alias 'eth3' on Armada XP mv78260Willy Tarreau1-1/+2
It was correctly set on mv78460 but not on mv78260, resulting in my OpenBlocks AX3-4 retrieving only 3 of its 4 MAC addresses from the boot loader. Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Cc: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Willy Tarreau <w@1wt.eu> Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-11-23ARM: mvebu: fix second and third PCIe unit of Armada XP mv78260Arnaud Ebalard1-24/+85
mv78260 flavour of Marvell Armada XP SoC has 3 PCIe units. The two first units are both x4 and quad x1 capable. The third unit is only x4 capable. This patch fixes mv78260 .dtsi to reflect those capabilities. Signed-off-by: Arnaud Ebalard <arno@natisbad.org> Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Cc: <stable@vger.kernel.org> # v3.10.x Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-09-30ARM: mvebu: link PCIe controllers to the MSI controllerThomas Petazzoni1-0/+1
This commit adjusts the Armada 370 and Armada XP PCIe controllers Device Tree informations to reference their MSI controller. In the case of this platform, the MSI controller is implemented by the MPIC. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Tested-by: Daniel Price <daniel.price@gmail.com> Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-08-29Merge tag 'dt-3.12' of git://git.infradead.org/linux-mvebu into next/socOlof Johansson1-3/+3
From Jason Cooper: mvebu dt changes for v3.12 - kirkwood - add ZyXEL NSA310 board, fan for ReadyNAS Duo v2 - mvebu - add ReadyNAS 102 board - misc dts updates and changes. v2: - dropped mv64xxx-i2c change * tag 'dt-3.12' of git://git.infradead.org/linux-mvebu: ARM: mvebu: Fix the Armada 370/XP timer compatible strings ARM: mvebu: use dts pre-processor for readynas 102 ARM: kirkwood: use dts pre-processor for nsa310 boards ARM: mvebu: use correct #interrupt-cells instead of #interrupts-cells ARM: Kirkwood: Add support for another ZyXEL NSA310 variant ARM: mvebu: Add Netgear ReadyNAS 102 board arm: kirkwood: readynas duo v2: Add GMT G762 Fan Controller Signed-off-by: Olof Johansson <olof@lixom.net> Conflicts: arch/arm/boot/dts/kirkwood-nsa310.dts
2013-08-16ARM: mvebu: use correct #interrupt-cells instead of #interrupts-cellsThomas Petazzoni1-3/+3
The Device Tree information for the GPIO banks of the Armada 370 and Armada XP SOCs was incorrectly using #interrupts-cells instead of controller when using GPIO interrupts, since the GPIO bank DT node wasn't recognized as a valid interrupt controller by the OF code. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-08-06ARM: mvebu: Relocate Armada 370/XP PCIe device tree nodesEzequiel Garcia1-122/+139
Now that mbus has been added to the device tree, it's possible to move the PCIe nodes out of internal registers, placing it directly below the mbus. This is a more accurate representation of the hardware. Moving the PCIe nodes, we now need to introduce an extra cell to encode the window target ID and attribute. Since this depends on the PCIe port, we split the ranges translation entries, to correspond to each MBus window. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Tested-by: Andrew Lunn <andrew@lunn.ch> Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-08-06ARM: mvebu: Use the preprocessor on Armada 370/XP device tree filesEzequiel Garcia1-1/+1
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Tested-by: Andrew Lunn <andrew@lunn.ch> Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-06-23ARM: mvebu: fix length of ethernet registers in mv78260 dtsiEzequiel Garcia1-1/+1
The length of the registers area for the Marvell 370/XP Ethernet controller was incorrect in the .dtsi: 0x2500, while it should have been 0x4000. This problem wasn't noticed because there used to be a static mapping for all the MMIO register region set up by ->map_io(). The register length was fixed in all the other device tree files, except from the armada-xp-mv78260.dtsi, in the following commit: commit cf8088c5cac6ce20d914b9131533844b9291a054 Author: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Date: Tue May 21 12:33:27 2013 +0200 arm: mvebu: fix length of Ethernet registers area in .dtsi This commit fixes a kernel panic in mvneta_probe(), when the kernel tries to access the unmapped registers: [ 163.639092] mvneta d0070000.ethernet eth0: mac: 6e:3c:4f:87:17:2e [ 163.646962] mvneta d0074000.ethernet eth1: mac: 6a:04:4e:6f:f5:ef [ 163.654853] mvneta d0030000.ethernet eth2: mac: 2a:99:19:19:fc:4c [ 163.661258] Unable to handle kernel paging request at virtual address f011bcf0 [ 163.668523] pgd = c0004000 [ 163.671237] [f011bcf0] *pgd=2f006811, *pte=00000000, *ppte=00000000 [ 163.677565] Internal error: Oops: 807 [#1] SMP ARM [ 163.682370] CPU: 0 PID: 1 Comm: swapper/0 Not tainted 3.10.0-rc6-01850-gba0682e #11 [ 163.690046] task: ef04c000 ti: ef03e000 task.ti: ef03e000 [ 163.695467] PC is at mvneta_probe+0x34c/0xabc [...] Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-04-15ARM: dts: mvebu: introduce internal-regs nodeGregory CLEMENT1-153/+155
Introduce a 'internal-regs' subnode, under which all devices are moved. This is not really needed for now, but will be for the mvebu-mbus driver. This generates a lot of code movement since it's indenting by one more tab all the devices. So it was a good opportunity to fix all the bad indentation. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-04-15ARM: dts: mvebu: Convert all the mvebu files to use the range propertyGregory CLEMENT1-22/+22
This conversion will allow to keep 32 bits addresses for the internal registers whereas the memory of the system will be 64 bits. Later it will also ease the move of the mvebu-mbus driver to the device tree support. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-04-15ARM: dts: mvebu: fix cpus section indentationThomas Petazzoni1-16/+16
Align the cpu node indentation with the rest of the file [gc]: added a commit description Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-04-15arm: mvebu: add PCIe Device Tree informations for Armada XPThomas Petazzoni1-0/+122
The Armada XP SoCs have multiple PCIe interfaces. The MV78230 has 2 PCIe units (one 4x or quad 1x, the other 1x only), the MV78260 has 3 PCIe units (two 4x or quad 1x and one 4x/1x), the MV78460 has 4 PCIe units (two 4x or quad 1x and two 4x/1x). We therefore add the necessary Device Tree informations to make those PCIe interfaces usable. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-02-28arm: mvebu: add pin muxing options for the SDIO interface on Armada XPThomas Petazzoni1-0/+6
The SDIO interface is only available on pins MPP30/31/32/33/34/35 on the various Armada XP variants, so we provide a pin muxing option for this in the Armada XP .dtsi files. Even though those muxing options are the same for MV78230, MV78260 and MV78460, we keep them in each .dtsi file, because the number of pins, and therefore the declaration of the pinctrl node, is different for each SoC variant. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-01-08arm: mvebu: use global interrupts for GPIOs on Armada XPThomas Petazzoni1-12/+9
The Armada XP GPIO controller has two ways of notifying interrupts: using global interrupts or using per-CPU interrupts. In an attempt to use the best available features, the 'marvell,armadaxp-gpio' compatible string selects a variant of the gpio-mvebu driver that makes use of the per-CPU interrupts. Unfortunately, this doesn't work properly in a SMP context, because we fall into cases where the GPIO interrupt is enabled on CPU X at the GPIO controller level, but on CPU Y at the interrupt controller level. It is not yet clear how to fix that easily. So for 3.8, our approach is to switch to global interrupts for GPIOs, so that we do not fall into this per-CPU interrupts problem. This patch therefore fixes GPIO interrupts on Armada XP platforms. Without this patch, GPIO interrupts simply do not work reliably, because their proper operation depends on which CPU the code requesting the interrupt is running. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-01-06arm: mvebu: Armada XP MV78230 has only three Ethernet interfacesThomas Petazzoni1-0/+8
We originally thought that the MV78230 variant of the Armada XP had four Ethernet interfaces, like the other variants MV78260 and MV78460. In fact, this is not true, and the MV78230 has only three Ethernet interfaces. So, the definitions of the Ethernet interfaces is now done as follows: * armada-370-xp.dtsi: definitions of the first two interfaces, that are common to Armada 370 and Armada XP * armada-xp.dtsi: definition of the third interface, common to all Armada XP variants. * armada-xp-mv78260.dtsi and armada-xp-mv78460.dtsi: definition of the fourth interface. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2012-11-20clk: armada-370-xp: add support for clock frameworkGregory CLEMENT1-0/+19
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Tested-by Gregory CLEMENT <gregory.clement@free-electrons.com>
2012-09-22arm: mvebu: add DT information for GPIO banks on Armada 370 and XPThomas Petazzoni1-0/+42
The gpioX aliases are needed so that the driver can use of_alias_get_id() to get a 0-based number of the GPIO bank, which we then use to compute the base GPIO of the bank being probed. This is similar to what gpio-mxs.c is doing. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Andrew Lunn <andrew@lunn.ch> Cc: Gregory Clement <gregory.clement@free-electrons.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2012-09-22ARM: mvebu: Add pinctrl support to Armada XP SoCsThomas Petazzoni1-0/+28
This commits adds the necessary device tree information to define the compatible property for the pinctrl driver instance of Armada XP SoCs. Until now, the device tree representation considered the Armada XP as a single SoC. But in fact, there are three different SoCs in the Armada XP families, with different number of CPU cores, different number of Ethernet interfaces... and different number of muxable pins or functions. We therefore introduce three armada-xp-mv78xx0.dtsi for the three SoCs of the Armada XP family. The current armada-xp-db.dts evaluation board uses the MV78460 variant of the SoC. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Reviewed-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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