diff options
Diffstat (limited to 'arch/arm')
117 files changed, 765 insertions, 2391 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 1d5ce138b877..fcedbb3c922d 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -279,7 +279,6 @@ config ARCH_INTEGRATOR select GENERIC_CLOCKEVENTS select PLAT_VERSATILE select PLAT_VERSATILE_FPGA_IRQ - select NEED_MACH_IO_H select NEED_MACH_MEMORY_H select SPARSE_IRQ select MULTI_IRQ_HANDLER @@ -312,7 +311,6 @@ config ARCH_VERSATILE select ICST select GENERIC_CLOCKEVENTS select ARCH_WANT_OPTIONAL_GPIOLIB - select NEED_MACH_IO_H if PCI select PLAT_VERSATILE select PLAT_VERSATILE_CLOCK select PLAT_VERSATILE_CLCD @@ -407,21 +405,19 @@ config ARCH_GEMINI help Support for the Cortina Systems Gemini family SoCs -config ARCH_PRIMA2 - bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform" - select CPU_V7 +config ARCH_SIRF + bool "CSR SiRF" select NO_IOPORT select ARCH_REQUIRE_GPIOLIB select GENERIC_CLOCKEVENTS - select CLKDEV_LOOKUP + select COMMON_CLK select GENERIC_IRQ_CHIP select MIGHT_HAVE_CACHE_L2X0 select PINCTRL select PINCTRL_SIRF select USE_OF - select ZONE_DMA help - Support for CSR SiRFSoC ARM Cortex A9 Platform + Support for CSR SiRFprimaII/Marco/Polo platforms config ARCH_EBSA110 bool "EBSA-110" @@ -456,7 +452,7 @@ config ARCH_FOOTBRIDGE select FOOTBRIDGE select GENERIC_CLOCKEVENTS select HAVE_IDE - select NEED_MACH_IO_H + select NEED_MACH_IO_H if !MMU select NEED_MACH_MEMORY_H help Support for systems based on the DC21285 companion chip @@ -513,7 +509,6 @@ config ARCH_IOP13XX select PCI select ARCH_SUPPORTS_MSI select VMSPLIT_1G - select NEED_MACH_IO_H select NEED_MACH_MEMORY_H select NEED_RET_TO_USER help @@ -523,7 +518,6 @@ config ARCH_IOP32X bool "IOP32x-based" depends on MMU select CPU_XSCALE - select NEED_MACH_IO_H select NEED_RET_TO_USER select PLAT_IOP select PCI @@ -536,7 +530,6 @@ config ARCH_IOP33X bool "IOP33x-based" depends on MMU select CPU_XSCALE - select NEED_MACH_IO_H select NEED_RET_TO_USER select PLAT_IOP select PCI @@ -576,7 +569,6 @@ config ARCH_DOVE select PCI select ARCH_REQUIRE_GPIOLIB select GENERIC_CLOCKEVENTS - select NEED_MACH_IO_H select PLAT_ORION help Support for the Marvell Dove SoC 88AP510 @@ -587,7 +579,6 @@ config ARCH_KIRKWOOD select PCI select ARCH_REQUIRE_GPIOLIB select GENERIC_CLOCKEVENTS - select NEED_MACH_IO_H select PLAT_ORION help Support for the following Marvell Kirkwood series SoCs: @@ -614,7 +605,6 @@ config ARCH_MV78XX0 select PCI select ARCH_REQUIRE_GPIOLIB select GENERIC_CLOCKEVENTS - select NEED_MACH_IO_H select PLAT_ORION help Support for the following Marvell MV78xx0 series SoCs: @@ -627,7 +617,6 @@ config ARCH_ORION5X select PCI select ARCH_REQUIRE_GPIOLIB select GENERIC_CLOCKEVENTS - select NEED_MACH_IO_H select PLAT_ORION help Support for the following Marvell Orion 5x series SoCs: @@ -683,7 +672,6 @@ config ARCH_TEGRA select HAVE_CLK select HAVE_SMP select MIGHT_HAVE_CACHE_L2X0 - select NEED_MACH_IO_H if PCI select ARCH_HAS_CPUFREQ select USE_OF help @@ -912,7 +900,6 @@ config ARCH_SHARK select PCI select ARCH_USES_GETTIMEOFFSET select NEED_MACH_MEMORY_H - select NEED_MACH_IO_H help Support for the StrongARM based Digital DNARD machine, also known as "Shark" (<http://www.shark-linux.de/shark.html>). @@ -931,6 +918,7 @@ config ARCH_U300 select COMMON_CLK select GENERIC_GPIO select ARCH_REQUIRE_GPIOLIB + select SPARSE_IRQ help Support for ST-Ericsson U300 series mobile platforms. @@ -1118,6 +1106,8 @@ source "arch/arm/mach-exynos/Kconfig" source "arch/arm/mach-shmobile/Kconfig" +source "arch/arm/mach-prima2/Kconfig" + source "arch/arm/mach-tegra/Kconfig" source "arch/arm/mach-u300/Kconfig" diff --git a/arch/arm/configs/prima2_defconfig b/arch/arm/configs/prima2_defconfig index c328ac65479a..807d4e2acb17 100644 --- a/arch/arm/configs/prima2_defconfig +++ b/arch/arm/configs/prima2_defconfig @@ -1,4 +1,6 @@ CONFIG_EXPERIMENTAL=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y CONFIG_RELAY=y CONFIG_BLK_DEV_INITRD=y CONFIG_KALLSYMS_ALL=y @@ -8,9 +10,7 @@ CONFIG_MODULE_UNLOAD=y CONFIG_PARTITION_ADVANCED=y CONFIG_BSD_DISKLABEL=y CONFIG_SOLARIS_X86_PARTITION=y -CONFIG_ARCH_PRIMA2=y -CONFIG_NO_HZ=y -CONFIG_HIGH_RES_TIMERS=y +CONFIG_ARCH_SIRF=y CONFIG_PREEMPT=y CONFIG_AEABI=y CONFIG_KEXEC=y @@ -36,7 +36,6 @@ CONFIG_SPI=y CONFIG_SPI_SIRF=y CONFIG_SPI_SPIDEV=y # CONFIG_HWMON is not set -# CONFIG_HID_SUPPORT is not set CONFIG_USB_GADGET=y CONFIG_USB_FILE_STORAGE=m CONFIG_USB_MASS_STORAGE=m diff --git a/arch/arm/include/asm/hardware/iop3xx.h b/arch/arm/include/asm/hardware/iop3xx.h index 2ff2c75a4639..02fe2fbe2477 100644 --- a/arch/arm/include/asm/hardware/iop3xx.h +++ b/arch/arm/include/asm/hardware/iop3xx.h @@ -217,18 +217,8 @@ extern int iop3xx_get_init_atu(void); #define IOP3XX_PCI_LOWER_MEM_PA 0x80000000 #define IOP3XX_PCI_MEM_WINDOW_SIZE 0x08000000 -#define IOP3XX_PCI_IO_WINDOW_SIZE 0x00010000 #define IOP3XX_PCI_LOWER_IO_PA 0x90000000 -#define IOP3XX_PCI_LOWER_IO_VA 0xfe000000 -#define IOP3XX_PCI_LOWER_IO_BA 0x90000000 -#define IOP3XX_PCI_UPPER_IO_PA (IOP3XX_PCI_LOWER_IO_PA +\ - IOP3XX_PCI_IO_WINDOW_SIZE - 1) -#define IOP3XX_PCI_UPPER_IO_VA (IOP3XX_PCI_LOWER_IO_VA +\ - IOP3XX_PCI_IO_WINDOW_SIZE - 1) -#define IOP3XX_PCI_IO_PHYS_TO_VIRT(addr) (((u32) (addr) -\ - IOP3XX_PCI_LOWER_IO_PA) +\ - IOP3XX_PCI_LOWER_IO_VA) - +#define IOP3XX_PCI_LOWER_IO_BA 0x00000000 #ifndef __ASSEMBLY__ diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h index 815c669fec0a..8f4db67533e5 100644 --- a/arch/arm/include/asm/io.h +++ b/arch/arm/include/asm/io.h @@ -113,11 +113,19 @@ static inline void __iomem *__typesafe_io(unsigned long addr) #define __iowmb() do { } while (0) #endif +/* PCI fixed i/o mapping */ +#define PCI_IO_VIRT_BASE 0xfee00000 + +extern int pci_ioremap_io(unsigned int offset, phys_addr_t phys_addr); + /* * Now, pick up the machine-defined IO definitions */ #ifdef CONFIG_NEED_MACH_IO_H #include <mach/io.h> +#elif defined(CONFIG_PCI) +#define IO_SPACE_LIMIT ((resource_size_t)0xfffff) +#define __io(a) __typesafe_io(PCI_IO_VIRT_BASE + ((a) & IO_SPACE_LIMIT)) #else #define __io(a) __typesafe_io((a) & IO_SPACE_LIMIT) #endif diff --git a/arch/arm/include/asm/mach/map.h b/arch/arm/include/asm/mach/map.h index a6efcdd6fd25..195ac2f9d3d3 100644 --- a/arch/arm/include/asm/mach/map.h +++ b/arch/arm/include/asm/mach/map.h @@ -9,6 +9,9 @@ * * Page table mapping constructs and function prototypes */ +#ifndef __ASM_MACH_MAP_H +#define __ASM_MACH_MAP_H + #include <asm/io.h> struct map_desc { @@ -34,6 +37,8 @@ struct map_desc { #ifdef CONFIG_MMU extern void iotable_init(struct map_desc *, int); +extern void vm_reserve_area_early(unsigned long addr, unsigned long size, + void *caller); struct mem_type; extern const struct mem_type *get_mem_type(unsigned int type); @@ -44,4 +49,7 @@ extern int ioremap_page(unsigned long virt, unsigned long phys, const struct mem_type *mtype); #else #define iotable_init(map,num) do { } while (0) +#define vm_reserve_area_early(a,s,c) do { } while (0) +#endif + #endif diff --git a/arch/arm/include/asm/mach/pci.h b/arch/arm/include/asm/mach/pci.h index 26c511fddf8f..db9fedb57f2c 100644 --- a/arch/arm/include/asm/mach/pci.h +++ b/arch/arm/include/asm/mach/pci.h @@ -11,6 +11,8 @@ #ifndef __ASM_MACH_PCI_H #define __ASM_MACH_PCI_H +#include <linux/ioport.h> + struct pci_sys_data; struct pci_ops; struct pci_bus; @@ -42,6 +44,8 @@ struct pci_sys_data { unsigned long io_offset; /* bus->cpu IO mapping offset */ struct pci_bus *bus; /* PCI bus */ struct list_head resources; /* root bus resources (apertures) */ + struct resource io_res; + char io_res_name[12]; /* Bridge swizzling */ u8 (*swizzle)(struct pci_dev *, u8 *); /* IRQ mapping */ @@ -55,6 +59,15 @@ struct pci_sys_data { void pci_common_init(struct hw_pci *); /* + * Setup early fixed I/O mapping. + */ +#if defined(CONFIG_PCI) +extern void pci_map_io_early(unsigned long pfn); +#else +static inline void pci_map_io_early(unsigned long pfn) {} +#endif + +/* * PCI controllers */ extern struct pci_ops iop3xx_ops; diff --git a/arch/arm/kernel/bios32.c b/arch/arm/kernel/bios32.c index 2b2f25e7fef5..b244696de1a3 100644 --- a/arch/arm/kernel/bios32.c +++ b/arch/arm/kernel/bios32.c @@ -13,6 +13,7 @@ #include <linux/io.h> #include <asm/mach-types.h> +#include <asm/mach/map.h> #include <asm/mach/pci.h> static int debug_pci; @@ -423,6 +424,38 @@ static int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) return irq; } +static int __init pcibios_init_resources(int busnr, struct pci_sys_data *sys) +{ + int ret; + struct pci_host_bridge_window *window; + + if (list_empty(&sys->resources)) { + pci_add_resource_offset(&sys->resources, + &iomem_resource, sys->mem_offset); + } + + list_for_each_entry(window, &sys->resources, list) { + if (resource_type(window->res) == IORESOURCE_IO) + return 0; + } + + sys->io_res.start = (busnr * SZ_64K) ? : pcibios_min_io; + sys->io_res.end = (busnr + 1) * SZ_64K - 1; + sys->io_res.flags = IORESOURCE_IO; + sys->io_res.name = sys->io_res_name; + sprintf(sys->io_res_name, "PCI%d I/O", busnr); + + ret = request_resource(&ioport_resource, &sys->io_res); + if (ret) { + pr_err("PCI: unable to allocate I/O port region (%d)\n", ret); + return ret; + } + pci_add_resource_offset(&sys->resources, &sys->io_res, + sys->io_offset); + + return 0; +} + static void __init pcibios_init_hw(struct hw_pci *hw, struct list_head *head) { struct pci_sys_data *sys = NULL; @@ -445,11 +478,10 @@ static void __init pcibios_init_hw(struct hw_pci *hw, struct list_head *head) ret = hw->setup(nr, sys); if (ret > 0) { - if (list_empty(&sys->resources)) { - pci_add_resource_offset(&sys->resources, - &ioport_resource, sys->io_offset); - pci_add_resource_offset(&sys->resources, - &iomem_resource, sys->mem_offset); + ret = pcibios_init_resources(nr, sys); + if (ret) { + kfree(sys); + break; } if (hw->scan) @@ -627,3 +659,15 @@ int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma, return 0; } + +void __init pci_map_io_early(unsigned long pfn) +{ + struct map_desc pci_io_desc = { + .virtual = PCI_IO_VIRT_BASE, + .type = MT_DEVICE, + .length = SZ_64K, + }; + + pci_io_desc.pfn = pfn; + iotable_init(&pci_io_desc, 1); +} diff --git a/arch/arm/mach-bcmring/arch.c b/arch/arm/mach-bcmring/arch.c index 76e795323569..c18a5048b6c5 100644 --- a/arch/arm/mach-bcmring/arch.c +++ b/arch/arm/mach-bcmring/arch.c @@ -37,7 +37,7 @@ #include <mach/csp/chipcHw_def.h> #include <mach/csp/chipcHw_inline.h> -#include <cfg_global.h> +#include <mach/cfg_global.h> #include "core.h" diff --git a/arch/arm/mach-bcmring/core.c b/arch/arm/mach-bcmring/core.c index adbfb1994582..4b50228a6771 100644 --- a/arch/arm/mach-bcmring/core.c +++ b/arch/arm/mach-bcmring/core.c @@ -43,11 +43,10 @@ #include <asm/mach/time.h> #include <asm/mach/map.h> -#include <cfg_global.h> +#include <mach/cfg_global.h> #include "clock.h" -#include <csp/secHw.h> #include <mach/csp/secHw_def.h> #include <mach/csp/chipcHw_inline.h> #include <mach/csp/tmrHw_reg.h> diff --git a/arch/arm/mach-bcmring/csp/chipc/chipcHw.c b/arch/arm/mach-bcmring/csp/chipc/chipcHw.c index 96273ff34956..5050833817b7 100644 --- a/arch/arm/mach-bcmring/csp/chipc/chipcHw.c +++ b/arch/arm/mach-bcmring/csp/chipc/chipcHw.c @@ -26,15 +26,15 @@ /* ---- Include Files ---------------------------------------------------- */ -#include <csp/errno.h> -#include <csp/stdint.h> -#include <csp/module.h> +#include <linux/errno.h> +#include <linux/types.h> +#include <linux/export.h> #include <mach/csp/chipcHw_def.h> #include <mach/csp/chipcHw_inline.h> -#include <csp/reg.h> -#include <csp/delay.h> +#include <mach/csp/reg.h> +#include <linux/delay.h> /* ---- Private Constants and Types --------------------------------------- */ @@ -61,21 +61,21 @@ static int chipcHw_divide(int num, int denom) /****************************************************************************/ chipcHw_freq chipcHw_getClockFrequency(chipcHw_CLOCK_e clock /* [ IN ] Configurable clock */ ) { - volatile uint32_t *pPLLReg = (uint32_t *) 0x0; - volatile uint32_t *pClockCtrl = (uint32_t *) 0x0; - volatile uint32_t *pDependentClock = (uint32_t *) 0x0; + uint32_t __iomem *pPLLReg = NULL; + uint32_t __iomem *pClockCtrl = NULL; + uint32_t __iomem *pDependentClock = NULL; uint32_t vcoFreqPll1Hz = 0; /* Effective VCO frequency for PLL1 in Hz */ uint32_t vcoFreqPll2Hz = 0; /* Effective VCO frequency for PLL2 in Hz */ uint32_t dependentClockType = 0; uint32_t vcoHz = 0; /* Get VCO frequencies */ - if ((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASK) != chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER) { + if ((readl(&pChipcHw->PLLPreDivider) & chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASK) != chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER) { uint64_t adjustFreq = 0; vcoFreqPll1Hz = chipcHw_XTAL_FREQ_Hz * chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) * - ((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >> + ((readl(&pChipcHw->PLLPreDivider) & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >> chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT); /* Adjusted frequency due to chipcHw_REG_PLL_DIVIDER_NDIV_f_SS */ @@ -86,13 +86,13 @@ chipcHw_freq chipcHw_getClockFrequency(chipcHw_CLOCK_e clock /* [ IN ] Configur } else { vcoFreqPll1Hz = chipcHw_XTAL_FREQ_Hz * chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) * - ((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >> + ((readl(&pChipcHw->PLLPreDivider) & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >> chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT); } vcoFreqPll2Hz = chipcHw_XTAL_FREQ_Hz * chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) * - ((pChipcHw->PLLPreDivider2 & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >> + ((readl(&pChipcHw->PLLPreDivider2) & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >> chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT); switch (clock) { @@ -187,51 +187,51 @@ chipcHw_freq chipcHw_getClockFrequency(chipcHw_CLOCK_e clock /* [ IN ] Configur if (pPLLReg) { /* Obtain PLL clock frequency */ - if (*pPLLReg & chipcHw_REG_PLL_CLOCK_BYPASS_SELECT) { + if (readl(pPLLReg) & chipcHw_REG_PLL_CLOCK_BYPASS_SELECT) { /* Return crystal clock frequency when bypassed */ return chipcHw_XTAL_FREQ_Hz; } else if (clock == chipcHw_CLOCK_DDR) { /* DDR frequency is configured in PLLDivider register */ - return chipcHw_divide (vcoHz, (((pChipcHw->PLLDivider & 0xFF000000) >> 24) ? ((pChipcHw->PLLDivider & 0xFF000000) >> 24) : 256)); + return chipcHw_divide (vcoHz, (((readl(&pChipcHw->PLLDivider) & 0xFF000000) >> 24) ? ((readl(&pChipcHw->PLLDivider) & 0xFF000000) >> 24) : 256)); } else { /* From chip revision number B0, LCD clock is internally divided by 2 */ if ((pPLLReg == &pChipcHw->LCDClock) && (chipcHw_getChipRevisionNumber() != chipcHw_REV_NUMBER_A0)) { vcoHz >>= 1; } /* Obtain PLL clock frequency using VCO dividers */ - return chipcHw_divide(vcoHz, ((*pPLLReg & chipcHw_REG_PLL_CLOCK_MDIV_MASK) ? (*pPLLReg & chipcHw_REG_PLL_CLOCK_MDIV_MASK) : 256)); + return chipcHw_divide(vcoHz, ((readl(pPLLReg) & chipcHw_REG_PLL_CLOCK_MDIV_MASK) ? (readl(pPLLReg) & chipcHw_REG_PLL_CLOCK_MDIV_MASK) : 256)); } } else if (pClockCtrl) { /* Obtain divider clock frequency */ uint32_t div; uint32_t freq = 0; - if (*pClockCtrl & chipcHw_REG_DIV_CLOCK_BYPASS_SELECT) { + if (readl(pClockCtrl) & chipcHw_REG_DIV_CLOCK_BYPASS_SELECT) { /* Return crystal clock frequency when bypassed */ return chipcHw_XTAL_FREQ_Hz; } else if (pDependentClock) { /* Identify the dependent clock frequency */ switch (dependentClockType) { case PLL_CLOCK: - if (*pDependentClock & chipcHw_REG_PLL_CLOCK_BYPASS_SELECT) { + if (readl(pDependentClock) & chipcHw_REG_PLL_CLOCK_BYPASS_SELECT) { /* Use crystal clock frequency when dependent PLL clock is bypassed */ freq = chipcHw_XTAL_FREQ_Hz; } else { /* Obtain PLL clock frequency using VCO dividers */ - div = *pDependentClock & chipcHw_REG_PLL_CLOCK_MDIV_MASK; + div = readl(pDependentClock) & chipcHw_REG_PLL_CLOCK_MDIV_MASK; freq = div ? chipcHw_divide(vcoHz, div) : 0; } break; case NON_PLL_CLOCK: - if (pDependentClock == (uint32_t *) &pChipcHw->ACLKClock) { + if (pDependentClock == &pChipcHw->ACLKClock) { freq = chipcHw_getClockFrequency (chipcHw_CLOCK_BUS); } else { - if (*pDependentClock & chipcHw_REG_DIV_CLOCK_BYPASS_SELECT) { + if (readl(pDependentClock) & chipcHw_REG_DIV_CLOCK_BYPASS_SELECT) { /* Use crystal clock frequency when dependent divider clock is bypassed */ freq = chipcHw_XTAL_FREQ_Hz; } else { /* Obtain divider clock frequency using XTAL dividers */ - div = *pDependentClock & chipcHw_REG_DIV_CLOCK_DIV_MASK; + div = readl(pDependentClock) & chipcHw_REG_DIV_CLOCK_DIV_MASK; freq = chipcHw_divide (chipcHw_XTAL_FREQ_Hz, (div ? div : 256)); } } @@ -242,7 +242,7 @@ chipcHw_freq chipcHw_getClockFrequency(chipcHw_CLOCK_e clock /* [ IN ] Configur freq = chipcHw_XTAL_FREQ_Hz; } - div = *pClockCtrl & chipcHw_REG_DIV_CLOCK_DIV_MASK; + div = readl(pClockCtrl) & chipcHw_REG_DIV_CLOCK_DIV_MASK; return chipcHw_divide(freq, (div ? div : 256)); } return 0; @@ -261,9 +261,9 @@ chipcHw_freq chipcHw_getClockFrequency(chipcHw_CLOCK_e clock /* [ IN ] Configur chipcHw_freq chipcHw_setClockFrequency(chipcHw_CLOCK_e clock, /* [ IN ] Configurable clock */ uint32_t freq /* [ IN ] Clock frequency in Hz */ ) { - volatile uint32_t *pPLLReg = (uint32_t *) 0x0; - volatile uint32_t *pClockCtrl = (uint32_t *) 0x0; - volatile uint32_t *pDependentClock = (uint32_t *) 0x0; + uint32_t __iomem *pPLLReg = NULL; + uint32_t __iomem *pClockCtrl = NULL; + uint32_t __iomem *pDependentClock = NULL; uint32_t vcoFreqPll1Hz = 0; /* Effective VCO frequency for PLL1 in Hz */ uint32_t desVcoFreqPll1Hz = 0; /* Desired VCO frequency for PLL1 in Hz */ uint32_t vcoFreqPll2Hz = 0; /* Effective VCO frequency for PLL2 in Hz */ @@ -272,12 +272,12 @@ chipcHw_freq chipcHw_setClockFrequency(chipcHw_CLOCK_e clock, /* [ IN ] Configu uint32_t desVcoHz = 0; /* Get VCO frequencies */ - if ((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASK) != chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER) { + if ((readl(&pChipcHw->PLLPreDivider) & chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASK) != chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER) { uint64_t adjustFreq = 0; vcoFreqPll1Hz = chipcHw_XTAL_FREQ_Hz * chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) * - ((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >> + ((readl(&pChipcHw->PLLPreDivider) & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >> chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT); /* Adjusted frequency due to chipcHw_REG_PLL_DIVIDER_NDIV_f_SS */ @@ -289,16 +289,16 @@ chipcHw_freq chipcHw_setClockFrequency(chipcHw_CLOCK_e clock, /* [ IN ] Configu /* Desired VCO frequency */ desVcoFreqPll1Hz = chipcHw_XTAL_FREQ_Hz * chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) * - (((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >> + (((readl(&pChipcHw->PLLPreDivider) & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >> chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT) + 1); } else { vcoFreqPll1Hz = desVcoFreqPll1Hz = chipcHw_XTAL_FREQ_Hz * chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) * - ((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >> + ((readl(&pChipcHw->PLLPreDivider) & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >> chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT); } vcoFreqPll2Hz = chipcHw_XTAL_FREQ_Hz * chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) * - ((pChipcHw->PLLPreDivider2 & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >> + ((readl(&pChipcHw->PLLPreDivider2) & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >> chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT); switch (clock) { @@ -307,8 +307,7 @@ chipcHw_freq chipcHw_setClockFrequency(chipcHw_CLOCK_e clock, /* [ IN ] Configu { REG_LOCAL_IRQ_SAVE; /* Dvide DDR_phy by two to obtain DDR_ctrl clock */ - pChipcHw->DDRClock = (pChipcHw->DDRClock & ~chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_MASK) | ((((freq / 2) / chipcHw_getClockFrequency(chipcHw_CLOCK_BUS)) - 1) - << chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_SHIFT); + writel((readl(&pChipcHw->DDRClock) & ~chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_MASK) | ((((freq / 2) / chipcHw_getClockFrequency(chipcHw_CLOCK_BUS)) - 1) << chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_SHIFT), &pChipcHw->DDRClock); REG_LOCAL_IRQ_RESTORE; } pPLLReg = &pChipcHw->DDRClock; @@ -329,8 +328,7 @@ chipcHw_freq chipcHw_setClockFrequency(chipcHw_CLOCK_e clock, /* [ IN ] Configu /* Configure the VPM:BUS ratio settings */ { REG_LOCAL_IRQ_SAVE; - pChipcHw->VPMClock = (pChipcHw->VPMClock & ~chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_MASK) | ((chipcHw_divide (freq, chipcHw_getClockFrequency(chipcHw_CLOCK_BUS)) - 1) - << chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_SHIFT); + writel((readl(&pChipcHw->VPMClock) & ~chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_MASK) | ((chipcHw_divide (freq, chipcHw_getClockFrequency(chipcHw_CLOCK_BUS)) - 1) << chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_SHIFT), &pChipcHw->VPMClock); REG_LOCAL_IRQ_RESTORE; } pPLLReg = &pChipcHw->VPMClock; @@ -428,9 +426,9 @@ chipcHw_freq chipcHw_setClockFrequency(chipcHw_CLOCK_e clock, /* [ IN ] Configu /* For DDR settings use only the PLL divider clock */ if (pPLLReg == &pChipcHw->DDRClock) { /* Set M1DIV for PLL1, which controls the DDR clock */ - reg32_write(&pChipcHw->PLLDivider, (pChipcHw->PLLDivider & 0x00FFFFFF) | ((chipcHw_REG_PLL_DIVIDER_MDIV (desVcoHz, freq)) << 24)); + reg32_write(&pChipcHw->PLLDivider, (readl(&pChipcHw->PLLDivider) & 0x00FFFFFF) | ((chipcHw_REG_PLL_DIVIDER_MDIV (desVcoHz, freq)) << 24)); /* Calculate expected frequency */ - freq = chipcHw_divide(vcoHz, (((pChipcHw->PLLDivider & 0xFF000000) >> 24) ? ((pChipcHw->PLLDivider & 0xFF000000) >> 24) : 256)); + freq = chipcHw_divide(vcoHz, (((readl(&pChipcHw->PLLDivider) & 0xFF000000) >> 24) ? ((readl(&pChipcHw->PLLDivider) & 0xFF000000) >> 24) : 256)); } else { /* From chip revision number B0, LCD clock is internally divided by 2 */ if ((pPLLReg == &pChipcHw->LCDClock) && (chipcHw_getChipRevisionNumber() != chipcHw_REV_NUMBER_A0)) { @@ -441,7 +439,7 @@ chipcHw_freq chipcHw_setClockFrequency(chipcHw_CLOCK_e clock, /* [ IN ] Configu reg32_modify_and(pPLLReg, ~(chipcHw_REG_PLL_CLOCK_MDIV_MASK)); reg32_modify_or(pPLLReg, chipcHw_REG_PLL_DIVIDER_MDIV(desVcoHz, freq)); /* Calculate expected frequency */ - freq = chipcHw_divide(vcoHz, ((*(pPLLReg) & chipcHw_REG_PLL_CLOCK_MDIV_MASK) ? (*(pPLLReg) & chipcHw_REG_PLL_CLOCK_MDIV_MASK) : 256)); + freq = chipcHw_divide(vcoHz, ((readl(pPLLReg) & chipcHw_REG_PLL_CLOCK_MDIV_MASK) ? (readl(pPLLReg) & chipcHw_REG_PLL_CLOCK_MDIV_MASK) : 256)); } /* Wait for for atleast 200ns as per the protocol to change frequency */ udelay(1); @@ -460,16 +458,16 @@ chipcHw_freq chipcHw_setClockFrequency(chipcHw_CLOCK_e clock, /* [ IN ] Configu if (pDependentClock) { switch (dependentClockType) { case PLL_CLOCK: - divider = chipcHw_divide(chipcHw_divide (desVcoHz, (*pDependentClock & chipcHw_REG_PLL_CLOCK_MDIV_MASK)), freq); + divider = chipcHw_divide(chipcHw_divide (desVcoHz, (readl(pDependentClock) & chipcHw_REG_PLL_CLOCK_MDIV_MASK)), freq); break; case NON_PLL_CLOCK: { uint32_t sourceClock = 0; - if (pDependentClock == (uint32_t *) &pChipcHw->ACLKClock) { + if (pDependentClock == &pChipcHw->ACLKClock) { sourceClock = chipcHw_getClockFrequency (chipcHw_CLOCK_BUS); } else { - uint32_t div = *pDependentClock & chipcHw_REG_DIV_CLOCK_DIV_MASK; + uint32_t div = readl(pDependentClock) & chipcHw_REG_DIV_CLOCK_DIV_MASK; sourceClock = chipcHw_divide (chipcHw_XTAL_FREQ_Hz, ((div) ? div : 256)); } divider = chipcHw_divide(sourceClock, freq); @@ -483,7 +481,7 @@ chipcHw_freq chipcHw_setClockFrequency(chipcHw_CLOCK_e clock, /* [ IN ] Configu if (divider) { REG_LOCAL_IRQ_SAVE; /* Set the divider to obtain the required frequency */ - *pClockCtrl = (*pClockCtrl & (~chipcHw_REG_DIV_CLOCK_DIV_MASK)) | (((divider > 256) ? chipcHw_REG_DIV_CLOCK_DIV_256 : divider) & chipcHw_REG_DIV_CLOCK_DIV_MASK); + writel((readl(pClockCtrl) & (~chipcHw_REG_DIV_CLOCK_DIV_MASK)) | (((divider > 256) ? chipcHw_REG_DIV_CLOCK_DIV_256 : divider) & chipcHw_REG_DIV_CLOCK_DIV_MASK), pClockCtrl); REG_LOCAL_IRQ_RESTORE; return freq; } @@ -515,25 +513,26 @@ static int vpmPhaseAlignA0(void) int count = 0; for (iter = 0; (iter < MAX_PHASE_ALIGN_ATTEMPTS) && (adjustCount < MAX_PHASE_ADJUST_COUNT); iter++) { - phaseControl = (pChipcHw->VPMClock & chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK) >> chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT; + phaseControl = (readl(&pChipcHw->VPMClock) & chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK) >> chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT; phaseValue = 0; prevPhaseComp = 0; /* Step 1: Look for falling PH_COMP transition */ /* Read the contents of VPM Clock resgister */ - phaseValue = pChipcHw->VPMClock; + phaseValue = readl(&pChipcHw->VPMClock); do { /* Store previous value of phase comparator */ prevPhaseComp = phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP; /* Change the value of PH_CTRL. */ - reg32_write(&pChipcHw->VPMClock, (pChipcHw->VPMClock & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT)); + reg32_write(&pChipcHw->VPMClock, + (readl(&pChipcHw->VPMClock) & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT)); /* Wait atleast 20 ns */ udelay(1); /* Toggle the LOAD_CH after phase control is written. */ - pChipcHw->VPMClock ^= chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE; + writel(readl(&pChipcHw->VPMClock) ^ chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE, &pChipcHw->VPMClock); /* Read the contents of VPM Clock resgister. */ - phaseValue = pChipcHw->VPMClock; + phaseValue = readl(&pChipcHw->VPMClock); if ((phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP) == 0x0) { phaseControl = (0x3F & (phaseControl - 1)); @@ -557,12 +556,13 @@ static int vpmPhaseAlignA0(void) for (count = 0; (count < 5) && ((phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP) == 0); count++) { phaseControl = (0x3F & (phaseControl + 1)); - reg32_write(&pChipcHw->VPMClock, (pChipcHw->VPMClock & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT)); + reg32_write(&pChipcHw->VPMClock, + (readl(&pChipcHw->VPMClock) & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT)); /* Wait atleast 20 ns */ udelay(1); /* Toggle the LOAD_CH after phase control is written. */ - pChipcHw->VPMClock ^= chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE; - phaseValue = pChipcHw->VPMClock; + writel(readl(&pChipcHw->VPMClock) ^ chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE, &pChipcHw->VPMClock); + phaseValue = readl(&pChipcHw->VPMClock); /* Count number of adjustment made */ adjustCount++; } @@ -581,12 +581,13 @@ static int vpmPhaseAlignA0(void) for (count = 0; (count < 3) && ((phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP) == 0); count++) { phaseControl = (0x3F & (phaseControl - 1)); - reg32_write(&pChipcHw->VPMClock, (pChipcHw->VPMClock & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT)); + reg32_write(&pChipcHw->VPMClock, + (readl(&pChipcHw->VPMClock) & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT)); /* Wait atleast 20 ns */ udelay(1); /* Toggle the LOAD_CH after phase control is written. */ - pChipcHw->VPMClock ^= chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE; - phaseValue = pChipcHw->VPMClock; + writel(readl(&pChipcHw->VPMClock) ^ chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE, &pChipcHw->VPMClock); + phaseValue = readl(&pChipcHw->VPMClock); /* Count number of adjustment made */ adjustCount++; } @@ -605,12 +606,13 @@ static int vpmPhaseAlignA0(void) for (count = 0; (count < 5); count++) { phaseControl = (0x3F & (phaseControl - 1)); - reg32_write(&pChipcHw->VPMClock, (pChipcHw->VPMClock & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT)); + reg32_write(&pChipcHw->VPMClock, + (readl(&pChipcHw->VPMClock) & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT)); /* Wait atleast 20 ns */ udelay(1); /* Toggle the LOAD_CH after phase control is written. */ - pChipcHw->VPMClock ^= chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE; - phaseValue = pChipcHw->VPMClock; + writel(readl(&pChipcHw->VPMClock) ^ chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE, &pChipcHw->VPMClock); + phaseValue = readl(&pChipcHw->VPMClock); /* Count number of adjustment made */ adjustCount++; } @@ -631,14 +633,14 @@ static int vpmPhaseAlignA0(void) /* Store previous value of phase comparator */ prevPhaseComp = phaseValue; /* Change the value of PH_CTRL. */ - reg32_write(&pChipcHw->VPMClock, (pChipcHw->VPMClock & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT)); + reg32_write(&pChipcHw->VPMClock, + (readl(&pChipcHw->VPMClock) & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT)); /* Wait atleast 20 ns */ udelay(1); /* Toggle the LOAD_CH after phase control is written. */ - pChipcHw->VPMClock ^= - chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE; + writel(readl(&pChipcHw->VPMClock) ^ chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE, &pChipcHw->VPMClock); /* Read the contents of VPM Clock resgister. */ - phaseValue = pChipcHw->VPMClock; + phaseValue = readl(&pChipcHw->VPMClock); if ((phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP) == 0x0) { phaseControl = (0x3F & (phaseControl - 1)); @@ -661,13 +663,13 @@ static int vpmPhaseAlignA0(void) } /* For VPM Phase should be perfectly aligned. */ - phaseControl = (((pChipcHw->VPMClock >> chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT) - 1) & 0x3F); + phaseControl = (((readl(&pChipcHw->VPMClock) >> chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT) - 1) & 0x3F); { REG_LOCAL_IRQ_SAVE; - pChipcHw->VPMClock = (pChipcHw->VPMClock & ~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT); + writel((readl(&pChipcHw->VPMClock) & ~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT), &pChipcHw->VPMClock); /* Load new phase value */ - pChipcHw->VPMClock ^= chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE; + writel(readl(&pChipcHw->VPMClock) ^ chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE, &pChipcHw->VPMClock); REG_LOCAL_IRQ_RESTORE; } @@ -697,7 +699,7 @@ int chipcHw_vpmPhaseAlign(void) int adjustCount = 0; /* Disable VPM access */ - pChipcHw->Spare1 &= ~chipcHw_REG_SPARE1_VPM_BUS_ACCESS_ENABLE; + writel(readl(&pChipcHw->Spare1) & ~chipcHw_REG_SPARE1_VPM_BUS_ACCESS_ENABLE, &pChipcHw->Spare1); /* Disable HW VPM phase alignment */ chipcHw_vpmHwPhaseAlignDisable(); /* Enable SW VPM phase alignment */ @@ -715,23 +717,24 @@ int chipcHw_vpmPhaseAlign(void) phaseControl--; } else { /* Enable VPM access */ - pChipcHw->Spare1 |= chipcHw_REG_SPARE1_VPM_BUS_ACCESS_ENABLE; + writel(readl(&pChipcHw->Spare1) | chipcHw_REG_SPARE1_VPM_BUS_ACCESS_ENABLE, &pChipcHw->Spare1); /* Return adjust count */ return adjustCount; } /* Change the value of PH_CTRL. */ - reg32_write(&pChipcHw->VPMClock, (pChipcHw->VPMClock & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT)); + reg32_write(&pChipcHw->VPMClock, + (readl(&pChipcHw->VPMClock) & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT)); /* Wait atleast 20 ns */ udelay(1); /* Toggle the LOAD_CH after phase control is written. */ - pChipcHw->VPMClock ^= chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE; + writel(readl(&pChipcHw->VPMClock) ^ chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE, &pChipcHw->VPMClock); /* Count adjustment */ adjustCount++; } } /* Disable VPM access */ - pChipcHw->Spare1 &= ~chipcHw_REG_SPARE1_VPM_BUS_ACCESS_ENABLE; + writel(readl(&pChipcHw->Spare1) & ~chipcHw_REG_SPARE1_VPM_BUS_ACCESS_ENABLE, &pChipcHw->Spare1); return -1; } diff --git a/arch/arm/mach-bcmring/csp/chipc/chipcHw_init.c b/arch/arm/mach-bcmring/csp/chipc/chipcHw_init.c index 367df75d4bb3..8377d8054168 100644 --- a/arch/arm/mach-bcmring/csp/chipc/chipcHw_init.c +++ b/arch/arm/mach-bcmring/csp/chipc/chipcHw_init.c @@ -26,15 +26,15 @@ /* ---- Include Files ---------------------------------------------------- */ -#include <csp/errno.h> -#include <csp/stdint.h> -#include <csp/module.h> +#include <linux/errno.h> +#include <linux/types.h> +#include <linux/export.h> #include <mach/csp/chipcHw_def.h> #include <mach/csp/chipcHw_inline.h> -#include <csp/reg.h> -#include <csp/delay.h> +#include <mach/csp/reg.h> +#include <linux/delay.h> /* ---- Private Constants and Types --------------------------------------- */ /* @@ -73,9 +73,9 @@ void chipcHw_pll2Enable(uint32_t vcoFreqHz) { REG_LOCAL_IRQ_SAVE; - pChipcHw->PLLConfig2 = - chipcHw_REG_PLL_CONFIG_D_RESET | - chipcHw_REG_PLL_CONFIG_A_RESET; + writel(chipcHw_REG_PLL_CONFIG_D_RESET | + chipcHw_REG_PLL_CONFIG_A_RESET, + &pChipcHw->PLLConfig2); pllPreDivider2 = chipcHw_REG_PLL_PREDIVIDER_POWER_DOWN | chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER | @@ -87,28 +87,30 @@ void chipcHw_pll2Enable(uint32_t vcoFreqHz) chipcHw_REG_PLL_PREDIVIDER_P2_SHIFT); /* Enable CHIPC registers to control the PLL */ - pChipcHw->PLLStatus |= chipcHw_REG_PLL_STATUS_CONTROL_ENABLE; + writel(readl(&pChipcHw->PLLStatus) | chipcHw_REG_PLL_STATUS_CONTROL_ENABLE, &pChipcHw->PLLStatus); /* Set pre divider to get desired VCO frequency */ - pChipcHw->PLLPreDivider2 = pllPreDivider2; + writel(pllPreDivider2, &pChipcHw->PLLPreDivider2); /* Set NDIV Frac */ - pChipcHw->PLLDivider2 = chipcHw_REG_PLL_DIVIDER_NDIV_f; + writel(chipcHw_REG_PLL_DIVIDER_NDIV_f, &pChipcHw->PLLDivider2); /* This has to be removed once the default values are fixed for PLL2. */ - pChipcHw->PLLControl12 = 0x38000700; - pChipcHw->PLLControl22 = 0x00000015; + writel(0x38000700, &pChipcHw->PLLControl12); + writel(0x00000015, &pChipcHw->PLLControl22); /* Reset PLL2 */ if (vcoFreqHz > chipcHw_REG_PLL_CONFIG_VCO_SPLIT_FREQ) { - pChipcHw->PLLConfig2 = chipcHw_REG_PLL_CONFIG_D_RESET | + writel(chipcHw_REG_PLL_CONFIG_D_RESET | chipcHw_REG_PLL_CONFIG_A_RESET | chipcHw_REG_PLL_CONFIG_VCO_1601_3200 | - chipcHw_REG_PLL_CONFIG_POWER_DOWN; + chipcHw_REG_PLL_CONFIG_POWER_DOWN, + &pChipcHw->PLLConfig2); } else { - pChipcHw->PLLConfig2 = chipcHw_REG_PLL_CONFIG_D_RESET | + writel(chipcHw_REG_PLL_CONFIG_D_RESET | chipcHw_REG_PLL_CONFIG_A_RESET | chipcHw_REG_PLL_CONFIG_VCO_800_1600 | - chipcHw_REG_PLL_CONFIG_POWER_DOWN; + chipcHw_REG_PLL_CONFIG_POWER_DOWN, + &pChipcHw->PLLConfig2); } REG_LOCAL_IRQ_RESTORE; } @@ -119,22 +121,25 @@ void chipcHw_pll2Enable(uint32_t vcoFreqHz) { REG_LOCAL_IRQ_SAVE; /* Remove analog reset and Power on the PLL */ - pChipcHw->PLLConfig2 &= + writel(readl(&pChipcHw->PLLConfig2) & ~(chipcHw_REG_PLL_CONFIG_A_RESET | - chipcHw_REG_PLL_CONFIG_POWER_DOWN); + chipcHw_REG_PLL_CONFIG_POWER_DOWN), + &pChipcHw->PLLConfig2); REG_LOCAL_IRQ_RESTORE; } /* Wait until PLL is locked */ - while (!(pChipcHw->PLLStatus2 & chipcHw_REG_PLL_STATUS_LOCKED)) + while (!(readl(&pChipcHw->PLLStatus2) & chipcHw_REG_PLL_STATUS_LOCKED)) ; { REG_LOCAL_IRQ_SAVE; /* Remove digital reset */ - pChipcHw->PLLConfig2 &= ~chipcHw_REG_PLL_CONFIG_D_RESET; + writel(readl(&pChipcHw->PLLConfig2) & + ~chipcHw_REG_PLL_CONFIG_D_RESET, + &pChipcHw->PLLConfig2); REG_LOCAL_IRQ_RESTORE; } @@ -157,9 +162,9 @@ void chipcHw_pll1Enable(uint32_t vcoFreqHz, chipcHw_SPREAD_SPECTRUM_e ssSupport) { REG_LOCAL_IRQ_SAVE; - pChipcHw->PLLConfig = - chipcHw_REG_PLL_CONFIG_D_RESET | - chipcHw_REG_PLL_CONFIG_A_RESET; + writel(chipcHw_REG_PLL_CONFIG_D_RESET | + chipcHw_REG_PLL_CONFIG_A_RESET, + &pChipcHw->PLLConfig); /* Setting VCO frequency */ if (ssSupport == chipcHw_SPREAD_SPECTRUM_ALLOW) { pllPreDivider = @@ -182,30 +187,22 @@ void chipcHw_pll1Enable(uint32_t vcoFreqHz, chipcHw_SPREAD_SPECTRUM_e ssSupport) } /* Enable CHIPC registers to control the PLL */ - pChipcHw->PLLStatus |= chipcHw_REG_PLL_STATUS_CONTROL_ENABLE; + writel(readl(&pChipcHw->PLLStatus) | chipcHw_REG_PLL_STATUS_CONTROL_ENABLE, &pChipcHw->PLLStatus); /* Set pre divider to get desired VCO frequency */ - pChipcHw->PLLPreDivider = pllPreDivider; + writel(pllPreDivider, &pChipcHw->PLLPreDivider); /* Set NDIV Frac */ if (ssSupport == chipcHw_SPREAD_SPECTRUM_ALLOW) { - pChipcHw->PLLDivider = chipcHw_REG_PLL_DIVIDER_M1DIV | - chipcHw_REG_PLL_DIVIDER_NDIV_f_SS; + writel(chipcHw_REG_PLL_DIVIDER_M1DIV | chipcHw_REG_PLL_DIVIDER_NDIV_f_SS, &pChipcHw->PLLDivider); } else { - pChipcHw->PLLDivider = chipcHw_REG_PLL_DIVIDER_M1DIV | - chipcHw_REG_PLL_DIVIDER_NDIV_f; + writel(chipcHw_REG_PLL_DIVIDER_M1DIV | chipcHw_REG_PLL_DIVIDER_NDIV_f, &pChipcHw->PLLDivider); } /* Reset PLL1 */ if (vcoFreqHz > chipcHw_REG_PLL_CONFIG_VCO_SPLIT_FREQ) { - pChipcHw->PLLConfig = chipcHw_REG_PLL_CONFIG_D_RESET | - chipcHw_REG_PLL_CONFIG_A_RESET | - chipcHw_REG_PLL_CONFIG_VCO_1601_3200 | - chipcHw_REG_PLL_CONFIG_POWER_DOWN; + writel(chipcHw_REG_PLL_CONFIG_D_RESET | chipcHw_REG_PLL_CONFIG_A_RESET | chipcHw_REG_PLL_CONFIG_VCO_1601_3200 | chipcHw_REG_PLL_CONFIG_POWER_DOWN, &pChipcHw->PLLConfig); } else { - pChipcHw->PLLConfig = chipcHw_REG_PLL_CONFIG_D_RESET | - chipcHw_REG_PLL_CONFIG_A_RESET | - chipcHw_REG_PLL_CONFIG_VCO_800_1600 | - chipcHw_REG_PLL_CONFIG_POWER_DOWN; + writel(chipcHw_REG_PLL_CONFIG_D_RESET | chipcHw_REG_PLL_CONFIG_A_RESET | chipcHw_REG_PLL_CONFIG_VCO_800_1600 | chipcHw_REG_PLL_CONFIG_POWER_DOWN, &pChipcHw->PLLConfig); } REG_LOCAL_IRQ_RESTORE; @@ -216,22 +213,19 @@ void chipcHw_pll1Enable(uint32_t vcoFreqHz, chipcHw_SPREAD_SPECTRUM_e ssSupport) { REG_LOCAL_IRQ_SAVE; /* Remove analog reset and Power on the PLL */ - pChipcHw->PLLConfig &= - ~(chipcHw_REG_PLL_CONFIG_A_RESET | - chipcHw_REG_PLL_CONFIG_POWER_DOWN); + writel(readl(&pChipcHw->PLLConfig) & ~(chipcHw_REG_PLL_CONFIG_A_RESET | chipcHw_REG_PLL_CONFIG_POWER_DOWN), &pChipcHw->PLLConfig); REG_LOCAL_IRQ_RESTORE; } /* Wait until PLL is locked */ - while (!(pChipcHw->PLLStatus & chipcHw_REG_PLL_STATUS_LOCKED) - || !(pChipcHw-> - PLLStatus2 & chipcHw_REG_PLL_STATUS_LOCKED)) + while (!(readl(&pChipcHw->PLLStatus) & chipcHw_REG_PLL_STATUS_LOCKED) + || !(readl(&pChipcHw->PLLStatus2) & chipcHw_REG_PLL_STATUS_LOCKED)) ; /* Remove digital reset */ { REG_LOCAL_IRQ_SAVE; - pChipcHw->PLLConfig &= ~chipcHw_REG_PLL_CONFIG_D_RESET; + writel(readl(&pChipcHw->PLLConfig) & ~chipcHw_REG_PLL_CONFIG_D_RESET, &pChipcHw->PLLConfig); REG_LOCAL_IRQ_RESTORE; } } @@ -267,11 +261,7 @@ void chipcHw_Init(chipcHw_INIT_PARAM_t *initParam /* [ IN ] Misc chip initializ chipcHw_clearStickyBits(chipcHw_REG_STICKY_CHIP_SOFT_RESET); /* Before configuring the ARM clock, atleast we need to make sure BUS clock maintains the proper ratio with ARM clock */ - pChipcHw->ACLKClock = - (pChipcHw-> - ACLKClock & ~chipcHw_REG_ACLKClock_CLK_DIV_MASK) | (initParam-> - armBusRatio & - chipcHw_REG_ACLKClock_CLK_DIV_MASK); + writel((readl(&pChipcHw->ACLKClock) & ~chipcHw_REG_ACLKClock_CLK_DIV_MASK) | (initParam-> armBusRatio & chipcHw_REG_ACLKClock_CLK_DIV_MASK), &pChipcHw->ACLKClock); /* Set various core component frequencies. The order in which this is done is important for some. */ /* The RTBUS (DDR PHY) is derived from the BUS, and the BUS from the ARM, and VPM needs to know BUS */ diff --git a/arch/arm/mach-bcmring/csp/chipc/chipcHw_reset.c b/arch/arm/mach-bcmring/csp/chipc/chipcHw_reset.c index 2671d8896bbb..f95ce913fa1e 100644 --- a/arch/arm/mach-bcmring/csp/chipc/chipcHw_reset.c +++ b/arch/arm/mach-bcmring/csp/chipc/chipcHw_reset.c @@ -13,11 +13,11 @@ *****************************************************************************/ /* ---- Include Files ---------------------------------------------------- */ -#include <csp/stdint.h> +#include <linux/types.h> #include <mach/csp/chipcHw_def.h> #include <mach/csp/chipcHw_inline.h> -#include <csp/intcHw.h> -#include <csp/cache.h> +#include <mach/csp/intcHw_reg.h> +#include <asm/cacheflush.h> /* ---- Private Constants and Types --------------------------------------- */ /* ---- Private Variables ------------------------------------------------- */ @@ -50,17 +50,18 @@ void chipcHw_reset(uint32_t mask) chipcHw_softReset(chipcHw_REG_SOFT_RESET_CHIP_SOFT); } /* Bypass the PLL clocks before reboot */ - pChipcHw->UARTClock |= chipcHw_REG_PLL_CLOCK_BYPASS_SELECT; - pChipcHw->SPIClock |= chipcHw_REG_PLL_CLOCK_BYPASS_SELECT; + writel(readl(&pChipcHw->UARTClock) | chipcHw_REG_PLL_CLOCK_BYPASS_SELECT, + &pChipcHw->UARTClock); + writel(readl(&pChipcHw->SPIClock) | chipcHw_REG_PLL_CLOCK_BYPASS_SELECT, + &pChipcHw->SPIClock); /* Copy the chipcHw_warmReset_run_from_aram function into ARAM */ do { - ((uint32_t *) MM_IO_BASE_ARAM)[i] = - ((uint32_t *) &chipcHw_reset_run_from_aram)[i]; + writel(((uint32_t *) &chipcHw_reset_run_from_aram)[i], ((uint32_t __iomem *) MM_IO_BASE_ARAM) + i); i++; - } while (((uint32_t *) MM_IO_BASE_ARAM)[i - 1] != 0xe1a0f00f); /* 0xe1a0f00f == asm ("mov r15, r15"); */ + } while (readl(((uint32_t __iomem*) MM_IO_BASE_ARAM) + i - 1) != 0xe1a0f00f); /* 0xe1a0f00f == asm ("mov r15, r15"); */ - CSP_CACHE_FLUSH_ALL; + flush_cache_all(); /* run the function from ARAM */ runFunc(); diff --git a/arch/arm/mach-bcmring/csp/dmac/dmacHw.c b/arch/arm/mach-bcmring/csp/dmac/dmacHw.c index 6b9be2e98e51..547f746c7ff4 100644 --- a/arch/arm/mach-bcmring/csp/dmac/dmacHw.c +++ b/arch/arm/mach-bcmring/csp/dmac/dmacHw.c @@ -25,11 +25,11 @@ /****************************************************************************/ /* ---- Include Files ---------------------------------------------------- */ -#include <csp/stdint.h> -#include <csp/string.h> -#include <stddef.h> +#include <linux/types.h> +#include <linux/string.h> +#include <linux/stddef.h> -#include <csp/dmacHw.h> +#include <mach/csp/dmacHw.h> #include <mach/csp/dmacHw_reg.h> #include <mach/csp/dmacHw_priv.h> #include <mach/csp/chipcHw_inline.h> @@ -55,33 +55,32 @@ static uint32_t GetFifoSize(dmacHw_HANDLE_t handle /* [ IN ] DMA Channel handl ) { uint32_t val = 0; dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle); - dmacHw_MISC_t *pMiscReg = - (dmacHw_MISC_t *) dmacHw_REG_MISC_BASE(pCblk->module); + dmacHw_MISC_t __iomem *pMiscReg = (void __iomem *)dmacHw_REG_MISC_BASE(pCblk->module); switch (pCblk->channel) { case 0: - val = (pMiscReg->CompParm2.lo & 0x70000000) >> 28; + val = (readl(&pMiscReg->CompParm2.lo) & 0x70000000) >> 28; break; case 1: - val = (pMiscReg->CompParm3.hi & 0x70000000) >> 28; + val = (readl(&pMiscReg->CompParm3.hi) & 0x70000000) >> 28; break; case 2: - val = (pMiscReg->CompParm3.lo & 0x70000000) >> 28; + val = (readl(&pMiscReg->CompParm3.lo) & 0x70000000) >> 28; break; case 3: - val = (pMiscReg->CompParm4.hi & 0x70000000) >> 28; + val = (readl(&pMiscReg->CompParm4.hi) & 0x70000000) >> 28; break; case 4: - val = (pMiscReg->CompParm4.lo & 0x70000000) >> 28; + val = (readl(&pMiscReg->CompParm4.lo) & 0x70000000) >> 28; break; case 5: - val = (pMiscReg->CompParm5.hi & 0x70000000) >> 28; + val = (readl(&pMiscReg->CompParm5.hi) & 0x70000000) >> 28; break; case 6: - val = (pMiscReg->CompParm5.lo & 0x70000000) >> 28; + val = (readl(&pMiscReg->CompParm5.lo) & 0x70000000) >> 28; break; case 7: - val = (pMiscReg->CompParm6.hi & 0x70000000) >> 28; + val = (readl(&pMiscReg->CompParm6.hi) & 0x70000000) >> 28; break; } diff --git a/arch/arm/mach-bcmring/csp/dmac/dmacHw_extra.c b/arch/arm/mach-bcmring/csp/dmac/dmacHw_extra.c index a1f328357aa4..fe438699d11e 100644 --- a/arch/arm/mach-bcmring/csp/dmac/dmacHw_extra.c +++ b/arch/arm/mach-bcmring/csp/dmac/dmacHw_extra.c @@ -26,10 +26,10 @@ /* ---- Include Files ---------------------------------------------------- */ -#include <csp/stdint.h> -#include <stddef.h> +#include <linux/types.h> +#include <linux/stddef.h> -#include <csp/dmacHw.h> +#include <mach/csp/dmacHw.h> #include <mach/csp/dmacHw_reg.h> #include <mach/csp/dmacHw_priv.h> diff --git a/arch/arm/mach-bcmring/csp/tmr/tmrHw.c b/arch/arm/mach-bcmring/csp/tmr/tmrHw.c index 16225e43f3c3..dc4137ff75ca 100644 --- a/arch/arm/mach-bcmring/csp/tmr/tmrHw.c +++ b/arch/arm/mach-bcmring/csp/tmr/tmrHw.c @@ -26,10 +26,10 @@ /* ---- Include Files ---------------------------------------------------- */ -#include <csp/errno.h> -#include <csp/stdint.h> +#include <linux/errno.h> +#include <linux/types.h> -#include <csp/tmrHw.h> +#include <mach/csp/tmrHw.h> #include <mach/csp/tmrHw_reg.h> #define tmrHw_ASSERT(a) if (!(a)) *(char *)0 = 0 diff --git a/arch/arm/mach-bcmring/include/cfg_global.h b/arch/arm/mach-bcmring/include/cfg_global.h deleted file mode 100644 index f01da877148e..000000000000 --- a/arch/arm/mach-bcmring/include/cfg_global.h +++ /dev/null @@ -1,13 +0,0 @@ -#ifndef _CFG_GLOBAL_H_ -#define _CFG_GLOBAL_H_ - -#include <cfg_global_defines.h> - -#define CFG_GLOBAL_CHIP BCM11107 -#define CFG_GLOBAL_CHIP_FAMILY CFG_GLOBAL_CHIP_FAMILY_BCMRING -#define CFG_GLOBAL_CHIP_REV 0xB0 -#define CFG_GLOBAL_RAM_SIZE 0x10000000 -#define CFG_GLOBAL_RAM_BASE 0x00000000 -#define CFG_GLOBAL_RAM_RESERVED_SIZE 0x000000 - -#endif /* _CFG_GLOBAL_H_ */ diff --git a/arch/arm/mach-bcmring/include/csp/cache.h b/arch/arm/mach-bcmring/include/csp/cache.h deleted file mode 100644 index caa20e59db99..000000000000 --- a/arch/arm/mach-bcmring/include/csp/cache.h +++ /dev/null @@ -1,35 +0,0 @@ -/***************************************************************************** -* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved. -* -* Unless you and Broadcom execute a separate written software license -* agreement governing use of this software, this software is licensed to you -* under the terms of the GNU General Public License version 2, available at -* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). -* -* Notwithstanding the above, under no circumstances may you combine this -* software in any way with any other Broadcom software provided under a -* license other than the GPL, without Broadcom's express prior written -* consent. -*****************************************************************************/ - -#ifndef CSP_CACHE_H -#define CSP_CACHE_H - -/* ---- Include Files ---------------------------------------------------- */ - -#include <csp/stdint.h> - -/* ---- Public Constants and Types --------------------------------------- */ - -#if defined(__KERNEL__) && !defined(STANDALONE) -#include <asm/cacheflush.h> - -#define CSP_CACHE_FLUSH_ALL flush_cache_all() - -#else - -#define CSP_CACHE_FLUSH_ALL - -#endif - -#endif /* CSP_CACHE_H */ diff --git a/arch/arm/mach-bcmring/include/csp/delay.h b/arch/arm/mach-bcmring/include/csp/delay.h deleted file mode 100644 index 8b3d80367293..000000000000 --- a/arch/arm/mach-bcmring/include/csp/delay.h +++ /dev/null @@ -1,36 +0,0 @@ -/***************************************************************************** -* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved. -* -* Unless you and Broadcom execute a separate written software license -* agreement governing use of this software, this software is licensed to you -* under the terms of the GNU General Public License version 2, available at -* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). -* -* Notwithstanding the above, under no circumstances may you combine this -* software in any way with any other Broadcom software provided under a -* license other than the GPL, without Broadcom's express prior written -* consent. -*****************************************************************************/ - - -#ifndef CSP_DELAY_H -#define CSP_DELAY_H - -/* ---- Include Files ---------------------------------------------------- */ - -/* Some CSP routines require use of the following delay routines. Use the OS */ -/* version if available, otherwise use a CSP specific definition. */ -/* void udelay(unsigned long usecs); */ -/* void mdelay(unsigned long msecs); */ - -#if defined(__KERNEL__) && !defined(STANDALONE) - #include <linux/delay.h> -#else - #include <mach/csp/delay.h> -#endif - -/* ---- Public Constants and Types --------------------------------------- */ -/* ---- Public Variable Externs ------------------------------------------ */ -/* ---- Public Function Prototypes --------------------------------------- */ - -#endif /* CSP_DELAY_H */ diff --git a/arch/arm/mach-bcmring/include/csp/errno.h b/arch/arm/mach-bcmring/include/csp/errno.h deleted file mode 100644 index 51357dd5b666..000000000000 --- a/arch/arm/mach-bcmring/include/csp/errno.h +++ /dev/null @@ -1,32 +0,0 @@ -/***************************************************************************** -* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved. -* -* Unless you and Broadcom execute a separate written software license -* agreement governing use of this software, this software is licensed to you -* under the terms of the GNU General Public License version 2, available at -* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). -* -* Notwithstanding the above, under no circumstances may you combine this -* software in any way with any other Broadcom software provided under a -* license other than the GPL, without Broadcom's express prior written -* consent. -*****************************************************************************/ - -#ifndef CSP_ERRNO_H -#define CSP_ERRNO_H - -/* ---- Include Files ---------------------------------------------------- */ - -#if defined(__KERNEL__) -#include <linux/errno.h> -#elif defined(CSP_SIMULATION) -#include <asm-generic/errno.h> -#else -#include <errno.h> -#endif - -/* ---- Public Constants and Types --------------------------------------- */ -/* ---- Public Variable Externs ------------------------------------------ */ -/* ---- Public Function Prototypes --------------------------------------- */ - -#endif /* CSP_ERRNO_H */ diff --git a/arch/arm/mach-bcmring/include/csp/intcHw.h b/arch/arm/mach-bcmring/include/csp/intcHw.h deleted file mode 100644 index 1c639c8ee08f..000000000000 --- a/arch/arm/mach-bcmring/include/csp/intcHw.h +++ /dev/null @@ -1,40 +0,0 @@ -/***************************************************************************** -* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved. -* -* Unless you and Broadcom execute a separate written software license -* agreement governing use of this software, this software is licensed to you -* under the terms of the GNU General Public License version 2, available at -* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). -* -* Notwithstanding the above, under no circumstances may you combine this -* software in any way with any other Broadcom software provided under a -* license other than the GPL, without Broadcom's express prior written -* consent. -*****************************************************************************/ - - -/****************************************************************************/ -/** -* @file intcHw.h -* -* @brief generic interrupt controller API -* -* @note -* None -*/ -/****************************************************************************/ - -#ifndef _INTCHW_H -#define _INTCHW_H - -/* ---- Include Files ---------------------------------------------------- */ -#include <mach/csp/intcHw_reg.h> - -/* ---- Public Constants and Types --------------------------------------- */ -/* ---- Public Variable Externs ------------------------------------------ */ -/* ---- Public Function Prototypes --------------------------------------- */ -static inline void intcHw_irq_disable(void *basep, uint32_t mask); -static inline void intcHw_irq_enable(void *basep, uint32_t mask); - -#endif /* _INTCHW_H */ - diff --git a/arch/arm/mach-bcmring/include/csp/module.h b/arch/arm/mach-bcmring/include/csp/module.h deleted file mode 100644 index c30d2a5975a6..000000000000 --- a/arch/arm/mach-bcmring/include/csp/module.h +++ /dev/null @@ -1,32 +0,0 @@ -/***************************************************************************** -* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved. -* -* Unless you and Broadcom execute a separate written software license -* agreement governing use of this software, this software is licensed to you -* under the terms of the GNU General Public License version 2, available at -* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). -* -* Notwithstanding the above, under no circumstances may you combine this -* software in any way with any other Broadcom software provided under a -* license other than the GPL, without Broadcom's express prior written -* consent. -*****************************************************************************/ - - -#ifndef CSP_MODULE_H -#define CSP_MODULE_H - -/* ---- Include Files ---------------------------------------------------- */ - -#ifdef __KERNEL__ - #include <linux/module.h> -#else - #define EXPORT_SYMBOL(symbol) -#endif - -/* ---- Public Constants and Types --------------------------------------- */ -/* ---- Public Variable Externs ------------------------------------------ */ -/* ---- Public Function Prototypes --------------------------------------- */ - - -#endif /* CSP_MODULE_H */ diff --git a/arch/arm/mach-bcmring/include/csp/secHw.h b/arch/arm/mach-bcmring/include/csp/secHw.h deleted file mode 100644 index b9d7e0732dfc..000000000000 --- a/arch/arm/mach-bcmring/include/csp/secHw.h +++ /dev/null @@ -1,65 +0,0 @@ -/***************************************************************************** -* Copyright 2004 - 2008 Broadcom Corporation. All rights reserved. -* -* Unless you and Broadcom execute a separate written software license -* agreement governing use of this software, this software is licensed to you -* under the terms of the GNU General Public License version 2, available at -* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). -* -* Notwithstanding the above, under no circumstances may you combine this -* software in any way with any other Broadcom software provided under a -* license other than the GPL, without Broadcom's express prior written -* consent. -*****************************************************************************/ - -/****************************************************************************/ -/** -* @file secHw.h -* -* @brief Definitions for accessing low level security features -* -*/ -/****************************************************************************/ -#ifndef SECHW_H -#define SECHW_H - -typedef void (*secHw_FUNC_t) (void); - -typedef enum { - secHw_MODE_SECURE = 0x0, /* Switches processor into secure mode */ - secHw_MODE_NONSECURE = 0x1 /* Switches processor into non-secure mode */ -} secHw_MODE; - -/****************************************************************************/ -/** -* @brief Requesting to execute the function in secure mode -* -* This function requests the given function to run in secure mode -* -*/ -/****************************************************************************/ -void secHw_RunSecure(secHw_FUNC_t /* Function to run in secure mode */ - ); - -/****************************************************************************/ -/** -* @brief Sets the mode -* -* his function sets the processor mode (secure/non-secure) -* -*/ -/****************************************************************************/ -void secHw_SetMode(secHw_MODE /* Processor mode */ - ); - -/****************************************************************************/ -/** -* @brief Get the current mode -* -* This function retieves the processor mode (secure/non-secure) -* -*/ -/****************************************************************************/ -void secHw_GetMode(secHw_MODE *); - -#endif /* SECHW_H */ diff --git a/arch/arm/mach-bcmring/include/csp/stdint.h b/arch/arm/mach-bcmring/include/csp/stdint.h deleted file mode 100644 index 3a8718bbf700..000000000000 --- a/arch/arm/mach-bcmring/include/csp/stdint.h +++ /dev/null @@ -1,30 +0,0 @@ -/***************************************************************************** -* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved. -* -* Unless you and Broadcom execute a separate written software license -* agreement governing use of this software, this software is licensed to you -* under the terms of the GNU General Public License version 2, available at -* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). -* -* Notwithstanding the above, under no circumstances may you combine this -* software in any way with any other Broadcom software provided under a -* license other than the GPL, without Broadcom's express prior written -* consent. -*****************************************************************************/ - -#ifndef CSP_STDINT_H -#define CSP_STDINT_H - -/* ---- Include Files ---------------------------------------------------- */ - -#ifdef __KERNEL__ -#include <linux/types.h> -#else -#include <stdint.h> -#endif - -/* ---- Public Constants and Types --------------------------------------- */ -/* ---- Public Variable Externs ------------------------------------------ */ -/* ---- Public Function Prototypes --------------------------------------- */ - -#endif /* CSP_STDINT_H */ diff --git a/arch/arm/mach-bcmring/include/csp/string.h b/arch/arm/mach-bcmring/include/csp/string.h deleted file mode 100644 index ad9e4005f141..000000000000 --- a/arch/arm/mach-bcmring/include/csp/string.h +++ /dev/null @@ -1,34 +0,0 @@ -/***************************************************************************** -* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved. -* -* Unless you and Broadcom execute a separate written software license -* agreement governing use of this software, this software is licensed to you -* under the terms of the GNU General Public License version 2, available at -* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). -* -* Notwithstanding the above, under no circumstances may you combine this -* software in any way with any other Broadcom software provided under a -* license other than the GPL, without Broadcom's express prior written -* consent. -*****************************************************************************/ - - - -#ifndef CSP_STRING_H -#define CSP_STRING_H - -/* ---- Include Files ---------------------------------------------------- */ - -#ifdef __KERNEL__ - #include <linux/string.h> -#else - #include <string.h> -#endif - -/* ---- Public Constants and Types --------------------------------------- */ -/* ---- Public Variable Externs ------------------------------------------ */ -/* ---- Public Function Prototypes --------------------------------------- */ - - -#endif /* CSP_STRING_H */ - diff --git a/arch/arm/mach-bcmring/include/cfg_global_defines.h b/arch/arm/mach-bcmring/include/mach/cfg_global.h index b5beb0b30734..449133eacdf5 100644 --- a/arch/arm/mach-bcmring/include/cfg_global_defines.h +++ b/arch/arm/mach-bcmring/include/mach/cfg_global.h @@ -38,3 +38,14 @@ #define IMAGE_HEADER_SIZE_CHECKSUM 4 #endif +#ifndef _CFG_GLOBAL_H_ +#define _CFG_GLOBAL_H_ + +#define CFG_GLOBAL_CHIP BCM11107 +#define CFG_GLOBAL_CHIP_FAMILY CFG_GLOBAL_CHIP_FAMILY_BCMRING +#define CFG_GLOBAL_CHIP_REV 0xB0 +#define CFG_GLOBAL_RAM_SIZE 0x10000000 +#define CFG_GLOBAL_RAM_BASE 0x00000000 +#define CFG_GLOBAL_RAM_RESERVED_SIZE 0x000000 + +#endif /* _CFG_GLOBAL_H_ */ diff --git a/arch/arm/mach-bcmring/include/mach/csp/cap_inline.h b/arch/arm/mach-bcmring/include/mach/csp/cap_inline.h index 933ce68ed90b..0a89e0c63419 100644 --- a/arch/arm/mach-bcmring/include/mach/csp/cap_inline.h +++ b/arch/arm/mach-bcmring/include/mach/csp/cap_inline.h @@ -17,7 +17,7 @@ /* ---- Include Files ---------------------------------------------------- */ #include <mach/csp/cap.h> -#include <cfg_global.h> +#include <mach/cfg_global.h> /* ---- Public Constants and Types --------------------------------------- */ #define CAP_CONFIG0_VPM_DIS 0x00000001 diff --git a/arch/arm/mach-bcmring/include/mach/csp/chipcHw_def.h b/arch/arm/mach-bcmring/include/mach/csp/chipcHw_def.h index 161973385faf..39f09cb89208 100644 --- a/arch/arm/mach-bcmring/include/mach/csp/chipcHw_def.h +++ b/arch/arm/mach-bcmring/include/mach/csp/chipcHw_def.h @@ -17,9 +17,9 @@ /* ---- Include Files ----------------------------------------------------- */ -#include <csp/stdint.h> -#include <csp/errno.h> -#include <csp/reg.h> +#include <linux/types.h> +#include <linux/errno.h> +#include <mach/csp/reg.h> #include <mach/csp/chipcHw_reg.h> /* ---- Public Constants and Types ---------------------------------------- */ diff --git a/arch/arm/mach-bcmring/include/mach/csp/chipcHw_inline.h b/arch/arm/mach-bcmring/include/mach/csp/chipcHw_inline.h index 03238c299001..a66f3f7abb86 100644 --- a/arch/arm/mach-bcmring/include/mach/csp/chipcHw_inline.h +++ b/arch/arm/mach-bcmring/include/mach/csp/chipcHw_inline.h @@ -17,8 +17,8 @@ /* ---- Include Files ----------------------------------------------------- */ -#include <csp/errno.h> -#include <csp/reg.h> +#include <linux/errno.h> +#include <mach/csp/reg.h> #include <mach/csp/chipcHw_reg.h> #include <mach/csp/chipcHw_def.h> @@ -47,7 +47,7 @@ static inline void chipcHw_setClock(chipcHw_CLOCK_e clock, /****************************************************************************/ static inline uint32_t chipcHw_getChipId(void) { - return pChipcHw->ChipId; + return readl(&pChipcHw->ChipId); } /****************************************************************************/ @@ -59,15 +59,16 @@ static inline uint32_t chipcHw_getChipId(void) /****************************************************************************/ static inline void chipcHw_enableSpreadSpectrum(void) { - if ((pChipcHw-> - PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASK) != + if ((readl(&pChipcHw-> + PLLPreDivider) & chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASK) != chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER) { - ddrcReg_PHY_ADDR_CTL_REGP->ssCfg = - (0xFFFF << ddrcReg_PHY_ADDR_SS_CFG_NDIV_AMPLITUDE_SHIFT) | + writel((0xFFFF << ddrcReg_PHY_ADDR_SS_CFG_NDIV_AMPLITUDE_SHIFT) | (ddrcReg_PHY_ADDR_SS_CFG_MIN_CYCLE_PER_TICK << - ddrcReg_PHY_ADDR_SS_CFG_CYCLE_PER_TICK_SHIFT); - ddrcReg_PHY_ADDR_CTL_REGP->ssCtl |= - ddrcReg_PHY_ADDR_SS_CTRL_ENABLE; + ddrcReg_PHY_ADDR_SS_CFG_CYCLE_PER_TICK_SHIFT), + &ddrcReg_PHY_ADDR_CTL_REGP->ssCfg); + writel(readl(&ddrcReg_PHY_ADDR_CTL_REGP->ssCtl) | + ddrcReg_PHY_ADDR_SS_CTRL_ENABLE, + &ddrcReg_PHY_ADDR_CTL_REGP->ssCtl); } } @@ -93,8 +94,8 @@ static inline void chipcHw_disableSpreadSpectrum(void) /****************************************************************************/ static inline uint32_t chipcHw_getChipProductId(void) { - return (pChipcHw-> - ChipId & chipcHw_REG_CHIPID_BASE_MASK) >> + return (readl(&pChipcHw-> + ChipId) & chipcHw_REG_CHIPID_BASE_MASK) >> chipcHw_REG_CHIPID_BASE_SHIFT; } @@ -109,7 +110,7 @@ static inline uint32_t chipcHw_getChipProductId(void) /****************************************************************************/ static inline chipcHw_REV_NUMBER_e chipcHw_getChipRevisionNumber(void) { - return pChipcHw->ChipId & chipcHw_REG_CHIPID_REV_MASK; + return readl(&pChipcHw->ChipId) & chipcHw_REG_CHIPID_REV_MASK; } /****************************************************************************/ @@ -156,7 +157,7 @@ static inline void chipcHw_busInterfaceClockDisable(uint32_t mask) /****************************************************************************/ static inline uint32_t chipcHw_getBusInterfaceClockStatus(void) { - return pChipcHw->BusIntfClock; + return readl(&pChipcHw->BusIntfClock); } /****************************************************************************/ @@ -215,8 +216,9 @@ static inline void chipcHw_softResetDisable(uint64_t mask) /* Deassert module soft reset */ REG_LOCAL_IRQ_SAVE; - pChipcHw->SoftReset1 ^= ctrl1; - pChipcHw->SoftReset2 ^= (ctrl2 & (~chipcHw_REG_SOFT_RESET_UNHOLD_MASK)); + writel(readl(&pChipcHw->SoftReset1) ^ ctrl1, &pChipcHw->SoftReset1); + writel(readl(&pChipcHw->SoftReset2) ^ (ctrl2 & + (~chipcHw_REG_SOFT_RESET_UNHOLD_MASK)), &pChipcHw->SoftReset2); REG_LOCAL_IRQ_RESTORE; } @@ -227,9 +229,10 @@ static inline void chipcHw_softResetEnable(uint64_t mask) uint32_t unhold = 0; REG_LOCAL_IRQ_SAVE; - pChipcHw->SoftReset1 |= ctrl1; + writel(readl(&pChipcHw->SoftReset1) | ctrl1, &pChipcHw->SoftReset1); /* Mask out unhold request bits */ - pChipcHw->SoftReset2 |= (ctrl2 & (~chipcHw_REG_SOFT_RESET_UNHOLD_MASK)); + writel(readl(&pChipcHw->SoftReset2) | (ctrl2 & + (~chipcHw_REG_SOFT_RESET_UNHOLD_MASK)), &pChipcHw->SoftReset2); /* Process unhold requests */ if (ctrl2 & chipcHw_REG_SOFT_RESET_VPM_GLOBAL_UNHOLD) { @@ -246,7 +249,7 @@ static inline void chipcHw_softResetEnable(uint64_t mask) if (unhold) { /* Make sure unhold request is effective */ - pChipcHw->SoftReset1 &= ~unhold; + writel(readl(&pChipcHw->SoftReset1) & ~unhold, &pChipcHw->SoftReset1); } REG_LOCAL_IRQ_RESTORE; } @@ -307,7 +310,7 @@ static inline void chipcHw_setOTPOption(uint64_t mask) /****************************************************************************/ static inline uint32_t chipcHw_getStickyBits(void) { - return pChipcHw->Sticky; + return readl(&pChipcHw->Sticky); } /****************************************************************************/ @@ -328,7 +331,7 @@ static inline void chipcHw_setStickyBits(uint32_t mask) bits |= chipcHw_REG_STICKY_POR_BROM; } else { uint32_t sticky; - sticky = pChipcHw->Sticky; + sticky = readl(pChipcHw->Sticky); if ((mask & chipcHw_REG_STICKY_BOOT_DONE) && (sticky & chipcHw_REG_STICKY_BOOT_DONE) == 0) { @@ -355,7 +358,7 @@ static inline void chipcHw_setStickyBits(uint32_t mask) bits |= chipcHw_REG_STICKY_GENERAL_5; } } - pChipcHw->Sticky = bits; + writel(bits, pChipcHw->Sticky); REG_LOCAL_IRQ_RESTORE; } @@ -377,7 +380,7 @@ static inline void chipcHw_clearStickyBits(uint32_t mask) (chipcHw_REG_STICKY_BOOT_DONE | chipcHw_REG_STICKY_GENERAL_1 | chipcHw_REG_STICKY_GENERAL_2 | chipcHw_REG_STICKY_GENERAL_3 | chipcHw_REG_STICKY_GENERAL_4 | chipcHw_REG_STICKY_GENERAL_5)) { - uint32_t sticky = pChipcHw->Sticky; + uint32_t sticky = readl(&pChipcHw->Sticky); if ((mask & chipcHw_REG_STICKY_BOOT_DONE) && (sticky & chipcHw_REG_STICKY_BOOT_DONE)) { @@ -410,7 +413,7 @@ static inline void chipcHw_clearStickyBits(uint32_t mask) mask &= ~chipcHw_REG_STICKY_GENERAL_5; } } - pChipcHw->Sticky = bits | mask; + writel(bits | mask, &pChipcHw->Sticky); REG_LOCAL_IRQ_RESTORE; } @@ -426,7 +429,7 @@ static inline void chipcHw_clearStickyBits(uint32_t mask) /****************************************************************************/ static inline uint32_t chipcHw_getSoftStraps(void) { - return pChipcHw->SoftStraps; + return readl(&pChipcHw->SoftStraps); } /****************************************************************************/ @@ -456,7 +459,7 @@ static inline void chipcHw_setSoftStraps(uint32_t strapOptions) /****************************************************************************/ static inline uint32_t chipcHw_getPinStraps(void) { - return pChipcHw->PinStraps; + return readl(&pChipcHw->PinStraps); } /****************************************************************************/ @@ -671,9 +674,9 @@ static inline void chipcHw_selectGE3(void) /****************************************************************************/ static inline chipcHw_GPIO_FUNCTION_e chipcHw_getGpioPinFunction(int pin) { - return (*((uint32_t *) chipcHw_REG_GPIO_MUX(pin)) & + return (readl(chipcHw_REG_GPIO_MUX(pin))) & (chipcHw_REG_GPIO_MUX_MASK << - chipcHw_REG_GPIO_MUX_POSITION(pin))) >> + chipcHw_REG_GPIO_MUX_POSITION(pin)) >> chipcHw_REG_GPIO_MUX_POSITION(pin); } @@ -841,8 +844,8 @@ static inline void chipcHw_setUsbDevice(void) static inline void chipcHw_setClock(chipcHw_CLOCK_e clock, chipcHw_OPTYPE_e type, int mode) { - volatile uint32_t *pPLLReg = (uint32_t *) 0x0; - volatile uint32_t *pClockCtrl = (uint32_t *) 0x0; + uint32_t __iomem *pPLLReg = NULL; + uint32_t __iomem *pClockCtrl = NULL; switch (clock) { case chipcHw_CLOCK_DDR: @@ -1071,7 +1074,7 @@ static inline void chipcHw_bypassClockDisable(chipcHw_CLOCK_e clock) /****************************************************************************/ static inline int chipcHw_isSoftwareStrapsEnable(void) { - return pChipcHw->SoftStraps & 0x00000001; + return readl(&pChipcHw->SoftStraps) & 0x00000001; } /****************************************************************************/ @@ -1138,7 +1141,7 @@ static inline void chipcHw_pll2TestDisable(void) /****************************************************************************/ static inline int chipcHw_isPllTestEnable(void) { - return pChipcHw->PLLConfig & chipcHw_REG_PLL_CONFIG_TEST_ENABLE; + return readl(&pChipcHw->PLLConfig) & chipcHw_REG_PLL_CONFIG_TEST_ENABLE; } /****************************************************************************/ @@ -1147,7 +1150,7 @@ static inline int chipcHw_isPllTestEnable(void) /****************************************************************************/ static inline int chipcHw_isPll2TestEnable(void) { - return pChipcHw->PLLConfig2 & chipcHw_REG_PLL_CONFIG_TEST_ENABLE; + return readl(&pChipcHw->PLLConfig2) & chipcHw_REG_PLL_CONFIG_TEST_ENABLE; } /****************************************************************************/ @@ -1183,8 +1186,8 @@ static inline void chipcHw_pll2TestSelect(uint32_t val) /****************************************************************************/ static inline uint8_t chipcHw_getPllTestSelected(void) { - return (uint8_t) ((pChipcHw-> - PLLConfig & chipcHw_REG_PLL_CONFIG_TEST_SELECT_MASK) + return (uint8_t) ((readl(&pChipcHw-> + PLLConfig) & chipcHw_REG_PLL_CONFIG_TEST_SELECT_MASK) >> chipcHw_REG_PLL_CONFIG_TEST_SELECT_SHIFT); } @@ -1194,8 +1197,8 @@ static inline uint8_t chipcHw_getPllTestSelected(void) /****************************************************************************/ static inline uint8_t chipcHw_getPll2TestSelected(void) { - return (uint8_t) ((pChipcHw-> - PLLConfig2 & chipcHw_REG_PLL_CONFIG_TEST_SELECT_MASK) + return (uint8_t) ((readl(&pChipcHw-> + PLLConfig2) & chipcHw_REG_PLL_CONFIG_TEST_SELECT_MASK) >> chipcHw_REG_PLL_CONFIG_TEST_SELECT_SHIFT); } @@ -1208,7 +1211,8 @@ static inline uint8_t chipcHw_getPll2TestSelected(void) static inline void chipcHw_pll1Disable(void) { REG_LOCAL_IRQ_SAVE; - pChipcHw->PLLConfig |= chipcHw_REG_PLL_CONFIG_POWER_DOWN; + writel(readl(&pChipcHw->PLLConfig) | chipcHw_REG_PLL_CONFIG_POWER_DOWN, + &pChipcHw->PLLConfig); REG_LOCAL_IRQ_RESTORE; } @@ -1221,7 +1225,8 @@ static inline void chipcHw_pll1Disable(void) static inline void chipcHw_pll2Disable(void) { REG_LOCAL_IRQ_SAVE; - pChipcHw->PLLConfig2 |= chipcHw_REG_PLL_CONFIG_POWER_DOWN; + writel(readl(&pChipcHw->PLLConfig2) | chipcHw_REG_PLL_CONFIG_POWER_DOWN, + &pChipcHw->PLLConfig2); REG_LOCAL_IRQ_RESTORE; } @@ -1233,7 +1238,8 @@ static inline void chipcHw_pll2Disable(void) static inline void chipcHw_ddrPhaseAlignInterruptEnable(void) { REG_LOCAL_IRQ_SAVE; - pChipcHw->Spare1 |= chipcHw_REG_SPARE1_DDR_PHASE_INTR_ENABLE; + writel(readl(&pChipcHw->Spare1) | chipcHw_REG_SPARE1_DDR_PHASE_INTR_ENABLE, + &pChipcHw->Spare1); REG_LOCAL_IRQ_RESTORE; } @@ -1245,7 +1251,8 @@ static inline void chipcHw_ddrPhaseAlignInterruptEnable(void) static inline void chipcHw_ddrPhaseAlignInterruptDisable(void) { REG_LOCAL_IRQ_SAVE; - pChipcHw->Spare1 &= ~chipcHw_REG_SPARE1_DDR_PHASE_INTR_ENABLE; + writel(readl(&pChipcHw->Spare1) & ~chipcHw_REG_SPARE1_DDR_PHASE_INTR_ENABLE, + &pChipcHw->Spare1); REG_LOCAL_IRQ_RESTORE; } @@ -1333,7 +1340,8 @@ static inline void chipcHw_ddrHwPhaseAlignDisable(void) static inline void chipcHw_vpmSwPhaseAlignEnable(void) { REG_LOCAL_IRQ_SAVE; - pChipcHw->VPMPhaseCtrl1 |= chipcHw_REG_VPM_SW_PHASE_CTRL_ENABLE; + writel(readl(&pChipcHw->VPMPhaseCtrl1) | chipcHw_REG_VPM_SW_PHASE_CTRL_ENABLE, + &pChipcHw->VPMPhaseCtrl1); REG_LOCAL_IRQ_RESTORE; } @@ -1372,7 +1380,8 @@ static inline void chipcHw_vpmHwPhaseAlignEnable(void) static inline void chipcHw_vpmHwPhaseAlignDisable(void) { REG_LOCAL_IRQ_SAVE; - pChipcHw->VPMPhaseCtrl1 &= ~chipcHw_REG_VPM_HW_PHASE_CTRL_ENABLE; + writel(readl(&pChipcHw->VPMPhaseCtrl1) & ~chipcHw_REG_VPM_HW_PHASE_CTRL_ENABLE, + &pChipcHw->VPMPhaseCtrl1); REG_LOCAL_IRQ_RESTORE; } @@ -1474,8 +1483,8 @@ chipcHw_setVpmHwPhaseAlignMargin(chipcHw_VPM_HW_PHASE_MARGIN_e margin) /****************************************************************************/ static inline uint32_t chipcHw_isDdrHwPhaseAligned(void) { - return (pChipcHw-> - PhaseAlignStatus & chipcHw_REG_DDR_PHASE_ALIGNED) ? 1 : 0; + return (readl(&pChipcHw-> + PhaseAlignStatus) & chipcHw_REG_DDR_PHASE_ALIGNED) ? 1 : 0; } /****************************************************************************/ @@ -1488,8 +1497,8 @@ static inline uint32_t chipcHw_isDdrHwPhaseAligned(void) /****************************************************************************/ static inline uint32_t chipcHw_isVpmHwPhaseAligned(void) { - return (pChipcHw-> - PhaseAlignStatus & chipcHw_REG_VPM_PHASE_ALIGNED) ? 1 : 0; + return (readl(&pChipcHw-> + PhaseAlignStatus) & chipcHw_REG_VPM_PHASE_ALIGNED) ? 1 : 0; } /****************************************************************************/ @@ -1500,8 +1509,8 @@ static inline uint32_t chipcHw_isVpmHwPhaseAligned(void) /****************************************************************************/ static inline uint32_t chipcHw_getDdrHwPhaseAlignStatus(void) { - return (pChipcHw-> - PhaseAlignStatus & chipcHw_REG_DDR_PHASE_STATUS_MASK) >> + return (readl(&pChipcHw-> + PhaseAlignStatus) & chipcHw_REG_DDR_PHASE_STATUS_MASK) >> chipcHw_REG_DDR_PHASE_STATUS_SHIFT; } @@ -1513,8 +1522,8 @@ static inline uint32_t chipcHw_getDdrHwPhaseAlignStatus(void) /****************************************************************************/ static inline uint32_t chipcHw_getVpmHwPhaseAlignStatus(void) { - return (pChipcHw-> - PhaseAlignStatus & chipcHw_REG_VPM_PHASE_STATUS_MASK) >> + return (readl(&pChipcHw-> + PhaseAlignStatus) & chipcHw_REG_VPM_PHASE_STATUS_MASK) >> chipcHw_REG_VPM_PHASE_STATUS_SHIFT; } @@ -1526,8 +1535,8 @@ static inline uint32_t chipcHw_getVpmHwPhaseAlignStatus(void) /****************************************************************************/ static inline uint32_t chipcHw_getDdrPhaseControl(void) { - return (pChipcHw-> - PhaseAlignStatus & chipcHw_REG_DDR_PHASE_CTRL_MASK) >> + return (readl(&pChipcHw-> + PhaseAlignStatus) & chipcHw_REG_DDR_PHASE_CTRL_MASK) >> chipcHw_REG_DDR_PHASE_CTRL_SHIFT; } @@ -1539,8 +1548,8 @@ static inline uint32_t chipcHw_getDdrPhaseControl(void) /****************************************************************************/ static inline uint32_t chipcHw_getVpmPhaseControl(void) { - return (pChipcHw-> - PhaseAlignStatus & chipcHw_REG_VPM_PHASE_CTRL_MASK) >> + return (readl(&pChipcHw-> + PhaseAlignStatus) & chipcHw_REG_VPM_PHASE_CTRL_MASK) >> chipcHw_REG_VPM_PHASE_CTRL_SHIFT; } diff --git a/arch/arm/mach-bcmring/include/mach/csp/chipcHw_reg.h b/arch/arm/mach-bcmring/include/mach/csp/chipcHw_reg.h index b162448f613c..26f5d0e4e1dd 100644 --- a/arch/arm/mach-bcmring/include/mach/csp/chipcHw_reg.h +++ b/arch/arm/mach-bcmring/include/mach/csp/chipcHw_reg.h @@ -24,7 +24,7 @@ #define CHIPCHW_REG_H #include <mach/csp/mm_io.h> -#include <csp/reg.h> +#include <mach/csp/reg.h> #include <mach/csp/ddrcReg.h> #define chipcHw_BASE_ADDRESS MM_IO_BASE_CHIPC @@ -131,8 +131,8 @@ typedef struct { uint32_t MiscInput_0_15; /* Input type for MISC 0 - 16 */ } chipcHw_REG_t; -#define pChipcHw ((volatile chipcHw_REG_t *) chipcHw_BASE_ADDRESS) -#define pChipcPhysical ((volatile chipcHw_REG_t *) MM_ADDR_IO_CHIPC) +#define pChipcHw ((chipcHw_REG_t __iomem *) chipcHw_BASE_ADDRESS) +#define pChipcPhysical (MM_ADDR_IO_CHIPC) #define chipcHw_REG_CHIPID_BASE_MASK 0xFFFFF000 #define chipcHw_REG_CHIPID_BASE_SHIFT 12 diff --git a/arch/arm/mach-bcmring/include/mach/csp/ddrcReg.h b/arch/arm/mach-bcmring/include/mach/csp/ddrcReg.h index f1b68e26fa6d..39da2c1fdafb 100644 --- a/arch/arm/mach-bcmring/include/mach/csp/ddrcReg.h +++ b/arch/arm/mach-bcmring/include/mach/csp/ddrcReg.h @@ -30,8 +30,8 @@ extern "C" { /* ---- Include Files ---------------------------------------------------- */ -#include <csp/reg.h> -#include <csp/stdint.h> +#include <mach/csp/reg.h> +#include <linux/types.h> #include <mach/csp/mm_io.h> @@ -416,7 +416,7 @@ extern "C" { } ddrcReg_PHY_ADDR_CTL_REG_t; #define ddrcReg_PHY_ADDR_CTL_REG_OFFSET 0x0400 -#define ddrcReg_PHY_ADDR_CTL_REGP ((volatile ddrcReg_PHY_ADDR_CTL_REG_t *) (MM_IO_BASE_DDRC + ddrcReg_PHY_ADDR_CTL_REG_OFFSET)) +#define ddrcReg_PHY_ADDR_CTL_REGP ((volatile ddrcReg_PHY_ADDR_CTL_REG_t __iomem*) (MM_IO_BASE_DDRC + ddrcReg_PHY_ADDR_CTL_REG_OFFSET)) /* @todo These SS definitions are duplicates of ones below */ diff --git a/arch/arm/mach-bcmring/include/csp/dmacHw.h b/arch/arm/mach-bcmring/include/mach/csp/dmacHw.h index e6a1dc484ca7..9dc90f46a84d 100644 --- a/arch/arm/mach-bcmring/include/csp/dmacHw.h +++ b/arch/arm/mach-bcmring/include/mach/csp/dmacHw.h @@ -23,9 +23,9 @@ #ifndef _DMACHW_H #define _DMACHW_H -#include <stddef.h> +#include <linux/stddef.h> -#include <csp/stdint.h> +#include <linux/types.h> #include <mach/csp/dmacHw_reg.h> /* Define DMA Channel ID using DMA controller number (m) and channel number (c). diff --git a/arch/arm/mach-bcmring/include/mach/csp/dmacHw_priv.h b/arch/arm/mach-bcmring/include/mach/csp/dmacHw_priv.h index d67e2f8c22de..9d9455e0c391 100644 --- a/arch/arm/mach-bcmring/include/mach/csp/dmacHw_priv.h +++ b/arch/arm/mach-bcmring/include/mach/csp/dmacHw_priv.h @@ -24,7 +24,7 @@ #ifndef _DMACHW_PRIV_H #define _DMACHW_PRIV_H -#include <csp/stdint.h> +#include <linux/types.h> /* Data type for DMA Link List Item */ typedef struct { diff --git a/arch/arm/mach-bcmring/include/mach/csp/dmacHw_reg.h b/arch/arm/mach-bcmring/include/mach/csp/dmacHw_reg.h index f1ecf96f2da5..7cd0aafa6f6e 100644 --- a/arch/arm/mach-bcmring/include/mach/csp/dmacHw_reg.h +++ b/arch/arm/mach-bcmring/include/mach/csp/dmacHw_reg.h @@ -24,7 +24,7 @@ #ifndef _DMACHW_REG_H #define _DMACHW_REG_H -#include <csp/stdint.h> +#include <linux/types.h> #include <mach/csp/mm_io.h> /* Data type for 64 bit little endian register */ @@ -121,75 +121,75 @@ typedef struct { } dmacHw_MISC_t; /* Base registers */ -#define dmacHw_0_MODULE_BASE_ADDR (char *) MM_IO_BASE_DMA0 /* DMAC 0 module's base address */ -#define dmacHw_1_MODULE_BASE_ADDR (char *) MM_IO_BASE_DMA1 /* DMAC 1 module's base address */ +#define dmacHw_0_MODULE_BASE_ADDR (char __iomem*) MM_IO_BASE_DMA0 /* DMAC 0 module's base address */ +#define dmacHw_1_MODULE_BASE_ADDR (char __iomem*) MM_IO_BASE_DMA1 /* DMAC 1 module's base address */ extern uint32_t dmaChannelCount_0; extern uint32_t dmaChannelCount_1; /* Define channel specific registers */ -#define dmacHw_CHAN_BASE(module, chan) ((dmacHw_CH_REG_t *) ((char *)((module) ? dmacHw_1_MODULE_BASE_ADDR : dmacHw_0_MODULE_BASE_ADDR) + ((chan) * sizeof(dmacHw_CH_REG_t)))) +#define dmacHw_CHAN_BASE(module, chan) ((dmacHw_CH_REG_t __iomem*) ((char __iomem*)((module) ? dmacHw_1_MODULE_BASE_ADDR : dmacHw_0_MODULE_BASE_ADDR) + ((chan) * sizeof(dmacHw_CH_REG_t)))) /* Raw interrupt status registers */ -#define dmacHw_REG_INT_RAW_BASE(module) ((char *)dmacHw_CHAN_BASE((module), ((module) ? dmaChannelCount_1 : dmaChannelCount_0))) -#define dmacHw_REG_INT_RAW_TRAN(module) (((dmacHw_INT_RAW_t *) dmacHw_REG_INT_RAW_BASE((module)))->RawTfr.lo) -#define dmacHw_REG_INT_RAW_BLOCK(module) (((dmacHw_INT_RAW_t *) dmacHw_REG_INT_RAW_BASE((module)))->RawBlock.lo) -#define dmacHw_REG_INT_RAW_STRAN(module) (((dmacHw_INT_RAW_t *) dmacHw_REG_INT_RAW_BASE((module)))->RawSrcTran.lo) -#define dmacHw_REG_INT_RAW_DTRAN(module) (((dmacHw_INT_RAW_t *) dmacHw_REG_INT_RAW_BASE((module)))->RawDstTran.lo) -#define dmacHw_REG_INT_RAW_ERROR(module) (((dmacHw_INT_RAW_t *) dmacHw_REG_INT_RAW_BASE((module)))->RawErr.lo) +#define dmacHw_REG_INT_RAW_BASE(module) ((char __iomem *)dmacHw_CHAN_BASE((module), ((module) ? dmaChannelCount_1 : dmaChannelCount_0))) +#define dmacHw_REG_INT_RAW_TRAN(module) (((dmacHw_INT_RAW_t __iomem *) dmacHw_REG_INT_RAW_BASE((module)))->RawTfr.lo) +#define dmacHw_REG_INT_RAW_BLOCK(module) (((dmacHw_INT_RAW_t __iomem *) dmacHw_REG_INT_RAW_BASE((module)))->RawBlock.lo) +#define dmacHw_REG_INT_RAW_STRAN(module) (((dmacHw_INT_RAW_t __iomem *) dmacHw_REG_INT_RAW_BASE((module)))->RawSrcTran.lo) +#define dmacHw_REG_INT_RAW_DTRAN(module) (((dmacHw_INT_RAW_t __iomem *) dmacHw_REG_INT_RAW_BASE((module)))->RawDstTran.lo) +#define dmacHw_REG_INT_RAW_ERROR(module) (((dmacHw_INT_RAW_t __iomem *) dmacHw_REG_INT_RAW_BASE((module)))->RawErr.lo) /* Interrupt status registers */ -#define dmacHw_REG_INT_STAT_BASE(module) ((char *)(dmacHw_REG_INT_RAW_BASE((module)) + sizeof(dmacHw_INT_RAW_t))) -#define dmacHw_REG_INT_STAT_TRAN(module) (((dmacHw_INT_STATUS_t *) dmacHw_REG_INT_STAT_BASE((module)))->StatusTfr.lo) -#define dmacHw_REG_INT_STAT_BLOCK(module) (((dmacHw_INT_STATUS_t *) dmacHw_REG_INT_STAT_BASE((module)))->StatusBlock.lo) -#define dmacHw_REG_INT_STAT_STRAN(module) (((dmacHw_INT_STATUS_t *) dmacHw_REG_INT_STAT_BASE((module)))->StatusSrcTran.lo) -#define dmacHw_REG_INT_STAT_DTRAN(module) (((dmacHw_INT_STATUS_t *) dmacHw_REG_INT_STAT_BASE((module)))->StatusDstTran.lo) -#define dmacHw_REG_INT_STAT_ERROR(module) (((dmacHw_INT_STATUS_t *) dmacHw_REG_INT_STAT_BASE((module)))->StatusErr.lo) +#define dmacHw_REG_INT_STAT_BASE(module) ((char __iomem*)(dmacHw_REG_INT_RAW_BASE((module)) + sizeof(dmacHw_INT_RAW_t))) +#define dmacHw_REG_INT_STAT_TRAN(module) (((dmacHw_INT_STATUS_t __iomem *) dmacHw_REG_INT_STAT_BASE((module)))->StatusTfr.lo) +#define dmacHw_REG_INT_STAT_BLOCK(module) (((dmacHw_INT_STATUS_t __iomem *) dmacHw_REG_INT_STAT_BASE((module)))->StatusBlock.lo) +#define dmacHw_REG_INT_STAT_STRAN(module) (((dmacHw_INT_STATUS_t __iomem *) dmacHw_REG_INT_STAT_BASE((module)))->StatusSrcTran.lo) +#define dmacHw_REG_INT_STAT_DTRAN(module) (((dmacHw_INT_STATUS_t __iomem *) dmacHw_REG_INT_STAT_BASE((module)))->StatusDstTran.lo) +#define dmacHw_REG_INT_STAT_ERROR(module) (((dmacHw_INT_STATUS_t __iomem *) dmacHw_REG_INT_STAT_BASE((module)))->StatusErr.lo) /* Interrupt status registers */ -#define dmacHw_REG_INT_MASK_BASE(module) ((char *)(dmacHw_REG_INT_STAT_BASE((module)) + sizeof(dmacHw_INT_STATUS_t))) -#define dmacHw_REG_INT_MASK_TRAN(module) (((dmacHw_INT_MASK_t *) dmacHw_REG_INT_MASK_BASE((module)))->MaskTfr.lo) -#define dmacHw_REG_INT_MASK_BLOCK(module) (((dmacHw_INT_MASK_t *) dmacHw_REG_INT_MASK_BASE((module)))->MaskBlock.lo) -#define dmacHw_REG_INT_MASK_STRAN(module) (((dmacHw_INT_MASK_t *) dmacHw_REG_INT_MASK_BASE((module)))->MaskSrcTran.lo) -#define dmacHw_REG_INT_MASK_DTRAN(module) (((dmacHw_INT_MASK_t *) dmacHw_REG_INT_MASK_BASE((module)))->MaskDstTran.lo) -#define dmacHw_REG_INT_MASK_ERROR(module) (((dmacHw_INT_MASK_t *) dmacHw_REG_INT_MASK_BASE((module)))->MaskErr.lo) +#define dmacHw_REG_INT_MASK_BASE(module) ((char __iomem*)(dmacHw_REG_INT_STAT_BASE((module)) + sizeof(dmacHw_INT_STATUS_t))) +#define dmacHw_REG_INT_MASK_TRAN(module) (((dmacHw_INT_MASK_t __iomem *) dmacHw_REG_INT_MASK_BASE((module)))->MaskTfr.lo) +#define dmacHw_REG_INT_MASK_BLOCK(module) (((dmacHw_INT_MASK_t __iomem *) dmacHw_REG_INT_MASK_BASE((module)))->MaskBlock.lo) +#define dmacHw_REG_INT_MASK_STRAN(module) (((dmacHw_INT_MASK_t __iomem *) dmacHw_REG_INT_MASK_BASE((module)))->MaskSrcTran.lo) +#define dmacHw_REG_INT_MASK_DTRAN(module) (((dmacHw_INT_MASK_t __iomem *) dmacHw_REG_INT_MASK_BASE((module)))->MaskDstTran.lo) +#define dmacHw_REG_INT_MASK_ERROR(module) (((dmacHw_INT_MASK_t __iomem *) dmacHw_REG_INT_MASK_BASE((module)))->MaskErr.lo) /* Interrupt clear registers */ -#define dmacHw_REG_INT_CLEAR_BASE(module) ((char *)(dmacHw_REG_INT_MASK_BASE((module)) + sizeof(dmacHw_INT_MASK_t))) -#define dmacHw_REG_INT_CLEAR_TRAN(module) (((dmacHw_INT_CLEAR_t *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearTfr.lo) -#define dmacHw_REG_INT_CLEAR_BLOCK(module) (((dmacHw_INT_CLEAR_t *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearBlock.lo) -#define dmacHw_REG_INT_CLEAR_STRAN(module) (((dmacHw_INT_CLEAR_t *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearSrcTran.lo) -#define dmacHw_REG_INT_CLEAR_DTRAN(module) (((dmacHw_INT_CLEAR_t *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearDstTran.lo) -#define dmacHw_REG_INT_CLEAR_ERROR(module) (((dmacHw_INT_CLEAR_t *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearErr.lo) -#define dmacHw_REG_INT_STATUS(module) (((dmacHw_INT_CLEAR_t *) dmacHw_REG_INT_CLEAR_BASE((module)))->StatusInt.lo) +#define dmacHw_REG_INT_CLEAR_BASE(module) ((char __iomem*)(dmacHw_REG_INT_MASK_BASE((module)) + sizeof(dmacHw_INT_MASK_t))) +#define dmacHw_REG_INT_CLEAR_TRAN(module) (((dmacHw_INT_CLEAR_t __iomem *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearTfr.lo) +#define dmacHw_REG_INT_CLEAR_BLOCK(module) (((dmacHw_INT_CLEAR_t __iomem *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearBlock.lo) +#define dmacHw_REG_INT_CLEAR_STRAN(module) (((dmacHw_INT_CLEAR_t __iomem *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearSrcTran.lo) +#define dmacHw_REG_INT_CLEAR_DTRAN(module) (((dmacHw_INT_CLEAR_t __iomem *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearDstTran.lo) +#define dmacHw_REG_INT_CLEAR_ERROR(module) (((dmacHw_INT_CLEAR_t __iomem *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearErr.lo) +#define dmacHw_REG_INT_STATUS(module) (((dmacHw_INT_CLEAR_t __iomem *) dmacHw_REG_INT_CLEAR_BASE((module)))->StatusInt.lo) /* Software handshaking registers */ -#define dmacHw_REG_SW_HS_BASE(module) ((char *)(dmacHw_REG_INT_CLEAR_BASE((module)) + sizeof(dmacHw_INT_CLEAR_t))) -#define dmacHw_REG_SW_HS_SRC_REQ(module) (((dmacHw_SW_HANDSHAKE_t *) dmacHw_REG_SW_HS_BASE((module)))->ReqSrcReg.lo) -#define dmacHw_REG_SW_HS_DST_REQ(module) (((dmacHw_SW_HANDSHAKE_t *) dmacHw_REG_SW_HS_BASE((module)))->ReqDstReg.lo) -#define dmacHw_REG_SW_HS_SRC_SGL_REQ(module) (((dmacHw_SW_HANDSHAKE_t *) dmacHw_REG_SW_HS_BASE((module)))->SglReqSrcReg.lo) -#define dmacHw_REG_SW_HS_DST_SGL_REQ(module) (((dmacHw_SW_HANDSHAKE_t *) dmacHw_REG_SW_HS_BASE((module)))->SglReqDstReg.lo) -#define dmacHw_REG_SW_HS_SRC_LST_REQ(module) (((dmacHw_SW_HANDSHAKE_t *) dmacHw_REG_SW_HS_BASE((module)))->LstSrcReg.lo) -#define dmacHw_REG_SW_HS_DST_LST_REQ(module) (((dmacHw_SW_HANDSHAKE_t *) dmacHw_REG_SW_HS_BASE((module)))->LstDstReg.lo) +#define dmacHw_REG_SW_HS_BASE(module) ((char __iomem*)(dmacHw_REG_INT_CLEAR_BASE((module)) + sizeof(dmacHw_INT_CLEAR_t))) +#define dmacHw_REG_SW_HS_SRC_REQ(module) (((dmacHw_SW_HANDSHAKE_t __iomem *) dmacHw_REG_SW_HS_BASE((module)))->ReqSrcReg.lo) +#define dmacHw_REG_SW_HS_DST_REQ(module) (((dmacHw_SW_HANDSHAKE_t __iomem *) dmacHw_REG_SW_HS_BASE((module)))->ReqDstReg.lo) +#define dmacHw_REG_SW_HS_SRC_SGL_REQ(module) (((dmacHw_SW_HANDSHAKE_t __iomem *) dmacHw_REG_SW_HS_BASE((module)))->SglReqSrcReg.lo) +#define dmacHw_REG_SW_HS_DST_SGL_REQ(module) (((dmacHw_SW_HANDSHAKE_t __iomem *) dmacHw_REG_SW_HS_BASE((module)))->SglReqDstReg.lo) +#define dmacHw_REG_SW_HS_SRC_LST_REQ(module) (((dmacHw_SW_HANDSHAKE_t __iomem *) dmacHw_REG_SW_HS_BASE((module)))->LstSrcReg.lo) +#define dmacHw_REG_SW_HS_DST_LST_REQ(module) (((dmacHw_SW_HANDSHAKE_t __iomem *) dmacHw_REG_SW_HS_BASE((module)))->LstDstReg.lo) /* Miscellaneous registers */ -#define dmacHw_REG_MISC_BASE(module) ((char *)(dmacHw_REG_SW_HS_BASE((module)) + sizeof(dmacHw_SW_HANDSHAKE_t))) -#define dmacHw_REG_MISC_CFG(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->DmaCfgReg.lo) -#define dmacHw_REG_MISC_CH_ENABLE(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->ChEnReg.lo) -#define dmacHw_REG_MISC_ID(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->DmaIdReg.lo) -#define dmacHw_REG_MISC_TEST(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->DmaTestReg.lo) -#define dmacHw_REG_MISC_COMP_PARAM1_LO(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm1.lo) -#define dmacHw_REG_MISC_COMP_PARAM1_HI(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm1.hi) -#define dmacHw_REG_MISC_COMP_PARAM2_LO(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm2.lo) -#define dmacHw_REG_MISC_COMP_PARAM2_HI(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm2.hi) -#define dmacHw_REG_MISC_COMP_PARAM3_LO(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm3.lo) -#define dmacHw_REG_MISC_COMP_PARAM3_HI(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm3.hi) -#define dmacHw_REG_MISC_COMP_PARAM4_LO(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm4.lo) -#define dmacHw_REG_MISC_COMP_PARAM4_HI(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm4.hi) -#define dmacHw_REG_MISC_COMP_PARAM5_LO(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm5.lo) -#define dmacHw_REG_MISC_COMP_PARAM5_HI(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm5.hi) -#define dmacHw_REG_MISC_COMP_PARAM6_LO(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm6.lo) -#define dmacHw_REG_MISC_COMP_PARAM6_HI(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm6.hi) +#define dmacHw_REG_MISC_BASE(module) ((char __iomem*)(dmacHw_REG_SW_HS_BASE((module)) + sizeof(dmacHw_SW_HANDSHAKE_t))) +#define dmacHw_REG_MISC_CFG(module) (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->DmaCfgReg.lo) +#define dmacHw_REG_MISC_CH_ENABLE(module) (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->ChEnReg.lo) +#define dmacHw_REG_MISC_ID(module) (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->DmaIdReg.lo) +#define dmacHw_REG_MISC_TEST(module) (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->DmaTestReg.lo) +#define dmacHw_REG_MISC_COMP_PARAM1_LO(module) (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm1.lo) +#define dmacHw_REG_MISC_COMP_PARAM1_HI(module) (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm1.hi) +#define dmacHw_REG_MISC_COMP_PARAM2_LO(module) (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm2.lo) +#define dmacHw_REG_MISC_COMP_PARAM2_HI(module) (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm2.hi) +#define dmacHw_REG_MISC_COMP_PARAM3_LO(module) (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm3.lo) +#define dmacHw_REG_MISC_COMP_PARAM3_HI(module) (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm3.hi) +#define dmacHw_REG_MISC_COMP_PARAM4_LO(module) (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm4.lo) +#define dmacHw_REG_MISC_COMP_PARAM4_HI(module) (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm4.hi) +#define dmacHw_REG_MISC_COMP_PARAM5_LO(module) (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm5.lo) +#define dmacHw_REG_MISC_COMP_PARAM5_HI(module) (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm5.hi) +#define dmacHw_REG_MISC_COMP_PARAM6_LO(module) (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm6.lo) +#define dmacHw_REG_MISC_COMP_PARAM6_HI(module) (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm6.hi) /* Channel control registers */ #define dmacHw_REG_SAR(module, chan) (dmacHw_CHAN_BASE((module), (chan))->ChannelSar.lo) diff --git a/arch/arm/mach-bcmring/include/mach/csp/hw_cfg.h b/arch/arm/mach-bcmring/include/mach/csp/hw_cfg.h index cfa91bed9d34..27f59dd27792 100644 --- a/arch/arm/mach-bcmring/include/mach/csp/hw_cfg.h +++ b/arch/arm/mach-bcmring/include/mach/csp/hw_cfg.h @@ -18,7 +18,7 @@ /* ---- Include Files ---------------------------------------------------- */ -#include <cfg_global.h> +#include <mach/cfg_global.h> #include <mach/csp/cap_inline.h> #if defined(__KERNEL__) diff --git a/arch/arm/mach-bcmring/include/mach/csp/intcHw_reg.h b/arch/arm/mach-bcmring/include/mach/csp/intcHw_reg.h index 0aeb6a6fe7f8..f59db25b5632 100644 --- a/arch/arm/mach-bcmring/include/mach/csp/intcHw_reg.h +++ b/arch/arm/mach-bcmring/include/mach/csp/intcHw_reg.h @@ -27,8 +27,8 @@ #define _INTCHW_REG_H /* ---- Include Files ---------------------------------------------------- */ -#include <csp/stdint.h> -#include <csp/reg.h> +#include <linux/types.h> +#include <mach/csp/reg.h> #include <mach/csp/mm_io.h> /* ---- Public Constants and Types --------------------------------------- */ @@ -37,9 +37,9 @@ #define INTCHW_NUM_INTC 3 /* Defines for interrupt controllers. This simplifies and cleans up the function calls. */ -#define INTCHW_INTC0 ((void *)MM_IO_BASE_INTC0) -#define INTCHW_INTC1 ((void *)MM_IO_BASE_INTC1) -#define INTCHW_SINTC ((void *)MM_IO_BASE_SINTC) +#define INTCHW_INTC0 (MM_IO_BASE_INTC0) +#define INTCHW_INTC1 (MM_IO_BASE_INTC1) +#define INTCHW_SINTC (MM_IO_BASE_SINTC) /* INTC0 - interrupt controller 0 */ #define INTCHW_INTC0_PIF_BITNUM 31 /* Peripheral interface interrupt */ @@ -232,15 +232,15 @@ /* ---- Public Variable Externs ------------------------------------------ */ /* ---- Public Function Prototypes --------------------------------------- */ /* Clear one or more IRQ interrupts. */ -static inline void intcHw_irq_disable(void *basep, uint32_t mask) +static inline void intcHw_irq_disable(void __iomem *basep, uint32_t mask) { - __REG32(basep + INTCHW_INTENCLEAR) = mask; + writel(mask, basep + INTCHW_INTENCLEAR); } /* Enables one or more IRQ interrupts. */ -static inline void intcHw_irq_enable(void *basep, uint32_t mask) +static inline void intcHw_irq_enable(void __iomem *basep, uint32_t mask) { - __REG32(basep + INTCHW_INTENABLE) = mask; + writel(mask, basep + INTCHW_INTENABLE); } #endif /* _INTCHW_REG_H */ diff --git a/arch/arm/mach-bcmring/include/mach/csp/mm_addr.h b/arch/arm/mach-bcmring/include/mach/csp/mm_addr.h index ad58cf873377..d571962f2904 100644 --- a/arch/arm/mach-bcmring/include/mach/csp/mm_addr.h +++ b/arch/arm/mach-bcmring/include/mach/csp/mm_addr.h @@ -29,7 +29,7 @@ /* ---- Include Files ---------------------------------------------------- */ #if !defined(CSP_SIMULATION) -#include <cfg_global.h> +#include <mach/cfg_global.h> #endif /* ---- Public Constants and Types --------------------------------------- */ diff --git a/arch/arm/mach-bcmring/include/mach/csp/mm_io.h b/arch/arm/mach-bcmring/include/mach/csp/mm_io.h index de92ec6a01aa..47450c23685a 100644 --- a/arch/arm/mach-bcmring/include/mach/csp/mm_io.h +++ b/arch/arm/mach-bcmring/include/mach/csp/mm_io.h @@ -30,7 +30,7 @@ #include <mach/csp/mm_addr.h> #if !defined(CSP_SIMULATION) -#include <cfg_global.h> +#include <mach/cfg_global.h> #endif /* ---- Public Constants and Types --------------------------------------- */ @@ -49,7 +49,7 @@ #ifdef __ASSEMBLY__ #define MM_IO_PHYS_TO_VIRT(phys) (0xF0000000 | (((phys) >> 4) & 0x0F000000) | ((phys) & 0xFFFFFF)) #else -#define MM_IO_PHYS_TO_VIRT(phys) (((phys) == MM_ADDR_IO_VPM_EXTMEM_RSVD) ? 0xF0000000 : \ +#define MM_IO_PHYS_TO_VIRT(phys) (void __iomem *)(((phys) == MM_ADDR_IO_VPM_EXTMEM_RSVD) ? 0xF0000000 : \ (0xF0000000 | (((phys) >> 4) & 0x0F000000) | ((phys) & 0xFFFFFF))) #endif #endif @@ -60,8 +60,8 @@ #ifdef __ASSEMBLY__ #define MM_IO_VIRT_TO_PHYS(virt) ((((virt) & 0x0F000000) << 4) | ((virt) & 0xFFFFFF)) #else -#define MM_IO_VIRT_TO_PHYS(virt) (((virt) == 0xF0000000) ? MM_ADDR_IO_VPM_EXTMEM_RSVD : \ - ((((virt) & 0x0F000000) << 4) | ((virt) & 0xFFFFFF))) +#define MM_IO_VIRT_TO_PHYS(virt) (((unsigned long)(virt) == 0xF0000000) ? MM_ADDR_IO_VPM_EXTMEM_RSVD : \ + ((((unsigned long)(virt) & 0x0F000000) << 4) | ((unsigned long)(virt) & 0xFFFFFF))) #endif #endif diff --git a/arch/arm/mach-bcmring/include/csp/reg.h b/arch/arm/mach-bcmring/include/mach/csp/reg.h index 56654d23c3d7..d9cbdca8cd25 100644 --- a/arch/arm/mach-bcmring/include/csp/reg.h +++ b/arch/arm/mach-bcmring/include/mach/csp/reg.h @@ -25,13 +25,14 @@ /* ---- Include Files ---------------------------------------------------- */ -#include <csp/stdint.h> +#include <linux/types.h> +#include <linux/io.h> /* ---- Public Constants and Types --------------------------------------- */ -#define __REG32(x) (*((volatile uint32_t *)(x))) -#define __REG16(x) (*((volatile uint16_t *)(x))) -#define __REG8(x) (*((volatile uint8_t *) (x))) +#define __REG32(x) (*((volatile uint32_t __iomem *)(x))) +#define __REG16(x) (*((volatile uint16_t __iomem *)(x))) +#define __REG8(x) (*((volatile uint8_t __iomem *) (x))) /* Macros used to define a sequence of reserved registers. The start / end */ /* are byte offsets in the particular register definition, with the "end" */ @@ -84,31 +85,31 @@ #endif -static inline void reg32_modify_and(volatile uint32_t *reg, uint32_t value) +static inline void reg32_modify_and(volatile uint32_t __iomem *reg, uint32_t value) { REG_LOCAL_IRQ_SAVE; - *reg &= value; + __raw_writel(__raw_readl(reg) & value, reg); REG_LOCAL_IRQ_RESTORE; } -static inline void reg32_modify_or(volatile uint32_t *reg, uint32_t value) +static inline void reg32_modify_or(volatile uint32_t __iomem *reg, uint32_t value) { REG_LOCAL_IRQ_SAVE; - *reg |= value; + __raw_writel(__raw_readl(reg) | value, reg); REG_LOCAL_IRQ_RESTORE; } -static inline void reg32_modify_mask(volatile uint32_t *reg, uint32_t mask, +static inline void reg32_modify_mask(volatile uint32_t __iomem *reg, uint32_t mask, uint32_t value) { REG_LOCAL_IRQ_SAVE; - *reg = (*reg & mask) | value; + __raw_writel((__raw_readl(reg) & mask) | value, reg); REG_LOCAL_IRQ_RESTORE; } -static inline void reg32_write(volatile uint32_t *reg, uint32_t value) +static inline void reg32_write(volatile uint32_t __iomem *reg, uint32_t value) { - *reg = value; + __raw_writel(value, reg); } #endif /* CSP_REG_H */ diff --git a/arch/arm/mach-bcmring/include/mach/csp/secHw_inline.h b/arch/arm/mach-bcmring/include/mach/csp/secHw_inline.h index 9cd6a032ab71..55d3cd4fd1e7 100644 --- a/arch/arm/mach-bcmring/include/mach/csp/secHw_inline.h +++ b/arch/arm/mach-bcmring/include/mach/csp/secHw_inline.h @@ -34,7 +34,7 @@ /****************************************************************************/ static inline void secHw_setSecure(uint32_t mask /* mask of type secHw_BLK_MASK_XXXXXX */ ) { - secHw_REGS_t *regp = (secHw_REGS_t *) MM_IO_BASE_TZPC; + secHw_REGS_t __iomem *regp = MM_IO_BASE_TZPC; if (mask & 0x0000FFFF) { regp->reg[secHw_IDX_LS].setSecure = mask & 0x0000FFFF; @@ -53,13 +53,13 @@ static inline void secHw_setSecure(uint32_t mask /* mask of type secHw_BLK_MASK /****************************************************************************/ static inline void secHw_setUnsecure(uint32_t mask /* mask of type secHw_BLK_MASK_XXXXXX */ ) { - secHw_REGS_t *regp = (secHw_REGS_t *) MM_IO_BASE_TZPC; + secHw_REGS_t __iomem *regp = MM_IO_BASE_TZPC; if (mask & 0x0000FFFF) { - regp->reg[secHw_IDX_LS].setUnsecure = mask & 0x0000FFFF; + writel(mask & 0x0000FFFF, ®p->reg[secHw_IDX_LS].setUnsecure); } if (mask & 0xFFFF0000) { - regp->reg[secHw_IDX_MS].setUnsecure = mask >> 16; + writel(mask >> 16, ®p->reg[secHw_IDX_MS].setUnsecure); } } @@ -71,7 +71,7 @@ static inline void secHw_setUnsecure(uint32_t mask /* mask of type secHw_BLK_MA /****************************************************************************/ static inline uint32_t secHw_getStatus(void) { - secHw_REGS_t *regp = (secHw_REGS_t *) MM_IO_BASE_TZPC; + secHw_REGS_t __iomem *regp = MM_IO_BASE_TZPC; return (regp->reg[1].status << 16) + regp->reg[0].status; } diff --git a/arch/arm/mach-bcmring/include/csp/tmrHw.h b/arch/arm/mach-bcmring/include/mach/csp/tmrHw.h index 2cbb530db8ea..1cc882ae60f5 100644 --- a/arch/arm/mach-bcmring/include/csp/tmrHw.h +++ b/arch/arm/mach-bcmring/include/mach/csp/tmrHw.h @@ -23,7 +23,7 @@ #ifndef _TMRHW_H #define _TMRHW_H -#include <csp/stdint.h> +#include <linux/types.h> typedef uint32_t tmrHw_ID_t; /* Timer ID */ typedef uint32_t tmrHw_COUNT_t; /* Timer count */ diff --git a/arch/arm/mach-bcmring/include/mach/dma.h b/arch/arm/mach-bcmring/include/mach/dma.h index 72543781207b..13e01384d6fc 100644 --- a/arch/arm/mach-bcmring/include/mach/dma.h +++ b/arch/arm/mach-bcmring/include/mach/dma.h @@ -27,7 +27,7 @@ #include <linux/kernel.h> #include <linux/semaphore.h> -#include <csp/dmacHw.h> +#include <mach/csp/dmacHw.h> #include <mach/timer.h> /* ---- Constants and Types ---------------------------------------------- */ diff --git a/arch/arm/mach-bcmring/include/mach/hardware.h b/arch/arm/mach-bcmring/include/mach/hardware.h index 6ae20a649a97..a0c92b4b8c60 100644 --- a/arch/arm/mach-bcmring/include/mach/hardware.h +++ b/arch/arm/mach-bcmring/include/mach/hardware.h @@ -22,7 +22,7 @@ #define __ASM_ARCH_HARDWARE_H #include <asm/sizes.h> -#include <cfg_global.h> +#include <mach/cfg_global.h> #include <mach/csp/mm_io.h> /* Hardware addresses of major areas. diff --git a/arch/arm/mach-bcmring/include/mach/reg_nand.h b/arch/arm/mach-bcmring/include/mach/reg_nand.h index 387376ffb56b..f8d51a8b0b15 100644 --- a/arch/arm/mach-bcmring/include/mach/reg_nand.h +++ b/arch/arm/mach-bcmring/include/mach/reg_nand.h @@ -30,7 +30,7 @@ #define __ASM_ARCH_REG_NAND_H /* ---- Include Files ---------------------------------------------------- */ -#include <csp/reg.h> +#include <mach/csp/reg.h> #include <mach/reg_umi.h> /* ---- Constants and Types ---------------------------------------------- */ diff --git a/arch/arm/mach-bcmring/include/mach/reg_umi.h b/arch/arm/mach-bcmring/include/mach/reg_umi.h index 0992842caa77..56dd9de7d83f 100644 --- a/arch/arm/mach-bcmring/include/mach/reg_umi.h +++ b/arch/arm/mach-bcmring/include/mach/reg_umi.h @@ -30,7 +30,7 @@ #define __ASM_ARCH_REG_UMI_H /* ---- Include Files ---------------------------------------------------- */ -#include <csp/reg.h> +#include <mach/csp/reg.h> #include <mach/csp/mm_io.h> /* ---- Constants and Types ---------------------------------------------- */ @@ -233,5 +233,5 @@ #define REG_UMI_BCH_ERR_LOC_WORD 0x00000018 /* location within a page (512 byte) */ #define REG_UMI_BCH_ERR_LOC_PAGE 0x00001FE0 -#define REG_UMI_BCH_ERR_LOC_ADDR(index) (__REG32(HW_UMI_BASE + 0x64 + (index / 2)*4) >> ((index % 2) * 16)) +#define REG_UMI_BCH_ERR_LOC_ADDR(index) (readl(HW_UMI_BASE + 0x64 + (index / 2)*4) >> ((index % 2) * 16)) #endif diff --git a/arch/arm/mach-bcmring/mm.c b/arch/arm/mach-bcmring/mm.c index 1adec78ec940..33824a81cac4 100644 --- a/arch/arm/mach-bcmring/mm.c +++ b/arch/arm/mach-bcmring/mm.c @@ -20,12 +20,12 @@ #include <mach/hardware.h> #include <mach/csp/mm_io.h> -#define IO_DESC(va, sz) { .virtual = va, \ +#define IO_DESC(va, sz) { .virtual = (unsigned long)va, \ .pfn = __phys_to_pfn(HW_IO_VIRT_TO_PHYS(va)), \ .length = sz, \ .type = MT_DEVICE } -#define MEM_DESC(va, sz) { .virtual = va, \ +#define MEM_DESC(va, sz) { .virtual = (unsigned long)va, \ .pfn = __phys_to_pfn(HW_IO_VIRT_TO_PHYS(va)), \ .length = sz, \ .type = MT_MEMORY } diff --git a/arch/arm/mach-bcmring/timer.c b/arch/arm/mach-bcmring/timer.c index af9c3d7e2a0c..59412903466e 100644 --- a/arch/arm/mach-bcmring/timer.c +++ b/arch/arm/mach-bcmring/timer.c @@ -14,7 +14,7 @@ #include <linux/types.h> #include <linux/module.h> -#include <csp/tmrHw.h> +#include <mach/csp/tmrHw.h> #include <mach/timer.h> /* The core.c file initializes timers 1 and 3 as a linux clocksource. */ diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c index 4db5de54b6a7..ed4fa5f316ea 100644 --- a/arch/arm/mach-dove/common.c +++ b/arch/arm/mach-dove/common.c @@ -49,16 +49,6 @@ static struct map_desc dove_io_desc[] __initdata = { .pfn = __phys_to_pfn(DOVE_NB_REGS_PHYS_BASE), .length = DOVE_NB_REGS_SIZE, .type = MT_DEVICE, - }, { - .virtual = DOVE_PCIE0_IO_VIRT_BASE, - .pfn = __phys_to_pfn(DOVE_PCIE0_IO_PHYS_BASE), - .length = DOVE_PCIE0_IO_SIZE, - .type = MT_DEVICE, - }, { - .virtual = DOVE_PCIE1_IO_VIRT_BASE, - .pfn = __phys_to_pfn(DOVE_PCIE1_IO_PHYS_BASE), - .length = DOVE_PCIE1_IO_SIZE, - .type = MT_DEVICE, }, }; diff --git a/arch/arm/mach-dove/include/mach/dove.h b/arch/arm/mach-dove/include/mach/dove.h index d52b0ef313b7..c91e3004a47b 100644 --- a/arch/arm/mach-dove/include/mach/dove.h +++ b/arch/arm/mach-dove/include/mach/dove.h @@ -50,14 +50,12 @@ #define DOVE_NB_REGS_SIZE SZ_8M #define DOVE_PCIE0_IO_PHYS_BASE 0xf2000000 -#define DOVE_PCIE0_IO_VIRT_BASE 0xfee00000 #define DOVE_PCIE0_IO_BUS_BASE 0x00000000 -#define DOVE_PCIE0_IO_SIZE SZ_1M +#define DOVE_PCIE0_IO_SIZE SZ_64K #define DOVE_PCIE1_IO_PHYS_BASE 0xf2100000 -#define DOVE_PCIE1_IO_VIRT_BASE 0xfef00000 -#define DOVE_PCIE1_IO_BUS_BASE 0x00100000 -#define DOVE_PCIE1_IO_SIZE SZ_1M +#define DOVE_PCIE1_IO_BUS_BASE 0x00010000 +#define DOVE_PCIE1_IO_SIZE SZ_64K /* * Dove Core Registers Map diff --git a/arch/arm/mach-dove/include/mach/io.h b/arch/arm/mach-dove/include/mach/io.h deleted file mode 100644 index 29c8b85355a5..000000000000 --- a/arch/arm/mach-dove/include/mach/io.h +++ /dev/null @@ -1,19 +0,0 @@ -/* - * arch/arm/mach-dove/include/mach/io.h - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef __ASM_ARCH_IO_H -#define __ASM_ARCH_IO_H - -#include "dove.h" - -#define IO_SPACE_LIMIT 0xffffffff - -#define __io(a) ((void __iomem *)(((a) - DOVE_PCIE0_IO_BUS_BASE) + \ - DOVE_PCIE0_IO_VIRT_BASE)) - -#endif diff --git a/arch/arm/mach-dove/pcie.c b/arch/arm/mach-dove/pcie.c index 47921b0cdc65..355332d502cb 100644 --- a/arch/arm/mach-dove/pcie.c +++ b/arch/arm/mach-dove/pcie.c @@ -26,9 +26,8 @@ struct pcie_port { u8 root_bus_nr; void __iomem *base; spinlock_t conf_lock; - char io_space_name[16]; char mem_space_name[16]; - struct resource res[2]; + struct resource res; }; static struct pcie_port pcie_port[2]; @@ -53,24 +52,10 @@ static int __init dove_pcie_setup(int nr, struct pci_sys_data *sys) orion_pcie_setup(pp->base); - /* - * IORESOURCE_IO - */ - snprintf(pp->io_space_name, sizeof(pp->io_space_name), - "PCIe %d I/O", pp->index); - pp->io_space_name[sizeof(pp->io_space_name) - 1] = 0; - pp->res[0].name = pp->io_space_name; - if (pp->index == 0) { - pp->res[0].start = DOVE_PCIE0_IO_PHYS_BASE; - pp->res[0].end = pp->res[0].start + DOVE_PCIE0_IO_SIZE - 1; - } else { - pp->res[0].start = DOVE_PCIE1_IO_PHYS_BASE; - pp->res[0].end = pp->res[0].start + DOVE_PCIE1_IO_SIZE - 1; - } - pp->res[0].flags = IORESOURCE_IO; - if (request_resource(&ioport_resource, &pp->res[0])) - panic("Request PCIe IO resource failed\n"); - pci_add_resource_offset(&sys->resources, &pp->res[0], sys->io_offset); + if (pp->index == 0) + pci_ioremap_io(sys->busnr * SZ_64K, DOVE_PCIE0_IO_PHYS_BASE); + else + pci_ioremap_io(sys->busnr * SZ_64K, DOVE_PCIE1_IO_PHYS_BASE); /* * IORESOURCE_MEM @@ -78,18 +63,18 @@ static int __init dove_pcie_setup(int nr, struct pci_sys_data *sys) snprintf(pp->mem_space_name, sizeof(pp->mem_space_name), "PCIe %d MEM", pp->index); pp->mem_space_name[sizeof(pp->mem_space_name) - 1] = 0; - pp->res[1].name = pp->mem_space_name; + pp->res.name = pp->mem_space_name; if (pp->index == 0) { - pp->res[1].start = DOVE_PCIE0_MEM_PHYS_BASE; - pp->res[1].end = pp->res[1].start + DOVE_PCIE0_MEM_SIZE - 1; + pp->res.start = DOVE_PCIE0_MEM_PHYS_BASE; + pp->res.end = pp->res.start + DOVE_PCIE0_MEM_SIZE - 1; } else { - pp->res[1].start = DOVE_PCIE1_MEM_PHYS_BASE; - pp->res[1].end = pp->res[1].start + DOVE_PCIE1_MEM_SIZE - 1; + pp->res.start = DOVE_PCIE1_MEM_PHYS_BASE; + pp->res.end = pp->res.start + DOVE_PCIE1_MEM_SIZE - 1; } - pp->res[1].flags = IORESOURCE_MEM; - if (request_resource(&iomem_resource, &pp->res[1])) + pp->res.flags = IORESOURCE_MEM; + if (request_resource(&iomem_resource, &pp->res)) panic("Request PCIe Memory resource failed\n"); - pci_add_resource_offset(&sys->resources, &pp->res[1], sys->mem_offset); + pci_add_resource_offset(&sys->resources, &pp->res, sys->mem_offset); return 1; } @@ -210,7 +195,7 @@ static void __init add_pcie_port(int index, unsigned long base) pp->root_bus_nr = -1; pp->base = (void __iomem *)base; spin_lock_init(&pp->conf_lock); - memset(pp->res, 0, sizeof(pp->res)); + memset(&pp->res, 0, sizeof(pp->res)); } else { printk(KERN_INFO "link down, ignoring\n"); } diff --git a/arch/arm/mach-footbridge/common.c b/arch/arm/mach-footbridge/common.c index 3e6aaa6361da..a42b369bc439 100644 --- a/arch/arm/mach-footbridge/common.c +++ b/arch/arm/mach-footbridge/common.c @@ -15,7 +15,7 @@ #include <linux/init.h> #include <linux/io.h> #include <linux/spinlock.h> - + #include <asm/pgtable.h> #include <asm/page.h> #include <asm/irq.h> @@ -26,6 +26,7 @@ #include <asm/mach/irq.h> #include <asm/mach/map.h> +#include <asm/mach/pci.h> #include "common.h" @@ -175,11 +176,6 @@ static struct map_desc ebsa285_host_io_desc[] __initdata = { .pfn = __phys_to_pfn(DC21285_PCI_IACK), .length = PCIIACK_SIZE, .type = MT_DEVICE, - }, { - .virtual = PCIO_BASE, - .pfn = __phys_to_pfn(DC21285_PCI_IO), - .length = PCIO_SIZE, - .type = MT_DEVICE, }, #endif }; @@ -196,8 +192,10 @@ void __init footbridge_map_io(void) * Now, work out what we've got to map in addition on this * platform. */ - if (footbridge_cfn_mode()) + if (footbridge_cfn_mode()) { iotable_init(ebsa285_host_io_desc, ARRAY_SIZE(ebsa285_host_io_desc)); + pci_map_io_early(__phys_to_pfn(DC21285_PCI_IO)); + } } void footbridge_restart(char mode, const char *cmd) diff --git a/arch/arm/mach-footbridge/dc21285.c b/arch/arm/mach-footbridge/dc21285.c index 9d62e3381024..a7cd2cf5e08d 100644 --- a/arch/arm/mach-footbridge/dc21285.c +++ b/arch/arm/mach-footbridge/dc21285.c @@ -276,8 +276,8 @@ int __init dc21285_setup(int nr, struct pci_sys_data *sys) sys->mem_offset = DC21285_PCI_MEM; - pci_add_resource_offset(&sys->resources, - &ioport_resource, sys->io_offset); + pci_ioremap_io(0, DC21285_PCI_IO); + pci_add_resource_offset(&sys->resources, &res[0], sys->mem_offset); pci_add_resource_offset(&sys->resources, &res[1], sys->mem_offset); @@ -298,7 +298,7 @@ void __init dc21285_preinit(void) mem_size = (unsigned int)high_memory - PAGE_OFFSET; for (mem_mask = 0x00100000; mem_mask < 0x10000000; mem_mask <<= 1) if (mem_mask >= mem_size) - break; + break; /* * These registers need to be set up whether we're the @@ -350,14 +350,6 @@ void __init dc21285_preinit(void) "PCI data parity", NULL); if (cfn_mode) { - static struct resource csrio; - - csrio.flags = IORESOURCE_IO; - csrio.name = "Footbridge"; - - allocate_resource(&ioport_resource, &csrio, 128, - 0xff00, 0xffff, 128, NULL, NULL); - /* * Map our SDRAM at a known address in PCI space, just in case * the firmware had other ideas. Using a nonzero base is @@ -365,7 +357,7 @@ void __init dc21285_preinit(void) * in the range 0x000a0000 to 0x000c0000. (eg, S3 cards). */ *CSR_PCICSRBASE = 0xf4000000; - *CSR_PCICSRIOBASE = csrio.start; + *CSR_PCICSRIOBASE = 0; *CSR_PCISDRAMBASE = __virt_to_bus(PAGE_OFFSET); *CSR_PCIROMBASE = 0; *CSR_PCICMD = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | diff --git a/arch/arm/mach-footbridge/include/mach/debug-macro.S b/arch/arm/mach-footbridge/include/mach/debug-macro.S index e5acde25ffc5..c169f0c99b2a 100644 --- a/arch/arm/mach-footbridge/include/mach/debug-macro.S +++ b/arch/arm/mach-footbridge/include/mach/debug-macro.S @@ -17,7 +17,8 @@ /* For NetWinder debugging */ .macro addruart, rp, rv, tmp mov \rp, #0x000003f8 - orr \rv, \rp, #0xff000000 @ virtual + orr \rv, \rp, #0xfe000000 @ virtual + orr \rv, \rv, #0x00e00000 @ virtual orr \rp, \rp, #0x7c000000 @ physical .endm diff --git a/arch/arm/mach-footbridge/include/mach/io.h b/arch/arm/mach-footbridge/include/mach/io.h index aba531eebbc6..aba46388cc0c 100644 --- a/arch/arm/mach-footbridge/include/mach/io.h +++ b/arch/arm/mach-footbridge/include/mach/io.h @@ -14,18 +14,10 @@ #ifndef __ASM_ARM_ARCH_IO_H #define __ASM_ARM_ARCH_IO_H -#ifdef CONFIG_MMU -#define MMU_IO(a, b) (a) -#else -#define MMU_IO(a, b) (b) -#endif - -#define PCIO_SIZE 0x00100000 -#define PCIO_BASE MMU_IO(0xff000000, 0x7c000000) - /* - * Translation of various region addresses to virtual addresses + * Translation of various i/o addresses to host addresses for !CONFIG_MMU */ +#define PCIO_BASE 0x7c000000 #define __io(a) ((void __iomem *)(PCIO_BASE + (a))) #endif diff --git a/arch/arm/mach-integrator/include/mach/io.h b/arch/arm/mach-integrator/include/mach/io.h deleted file mode 100644 index 8de70de3dd0a..000000000000 --- a/arch/arm/mach-integrator/include/mach/io.h +++ /dev/null @@ -1,33 +0,0 @@ -/* - * arch/arm/mach-integrator/include/mach/io.h - * - * Copyright (C) 1999 ARM Limited - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#ifndef __ASM_ARM_ARCH_IO_H -#define __ASM_ARM_ARCH_IO_H - -/* - * WARNING: this has to mirror definitions in platform.h - */ -#define PCI_MEMORY_VADDR 0xe8000000 -#define PCI_CONFIG_VADDR 0xec000000 -#define PCI_V3_VADDR 0xed000000 -#define PCI_IO_VADDR 0xee000000 - -#define __io(a) ((void __iomem *)(PCI_IO_VADDR + (a))) - -#endif diff --git a/arch/arm/mach-integrator/include/mach/platform.h b/arch/arm/mach-integrator/include/mach/platform.h index ec467baade09..4c0347526851 100644 --- a/arch/arm/mach-integrator/include/mach/platform.h +++ b/arch/arm/mach-integrator/include/mach/platform.h @@ -324,6 +324,10 @@ */ #define PHYS_PCI_V3_BASE 0x62000000 +#define PCI_MEMORY_VADDR 0xe8000000 +#define PCI_CONFIG_VADDR 0xec000000 +#define PCI_V3_VADDR 0xed000000 + /* ------------------------------------------------------------------------ * Integrator Interrupt Controllers * ------------------------------------------------------------------------ diff --git a/arch/arm/mach-integrator/integrator_ap.c b/arch/arm/mach-integrator/integrator_ap.c index 3b2267529f5e..fd3ef28d2c1a 100644 --- a/arch/arm/mach-integrator/integrator_ap.c +++ b/arch/arm/mach-integrator/integrator_ap.c @@ -50,6 +50,7 @@ #include <asm/mach/arch.h> #include <asm/mach/irq.h> #include <asm/mach/map.h> +#include <asm/mach/pci.h> #include <asm/mach/time.h> #include <plat/fpga-irq.h> @@ -73,7 +74,7 @@ * e8000000 40000000 PCI memory PHYS_PCI_MEM_BASE (max 512M) * ec000000 61000000 PCI config space PHYS_PCI_CONFIG_BASE (max 16M) * ed000000 62000000 PCI V3 regs PHYS_PCI_V3_BASE (max 64k) - * ee000000 60000000 PCI IO PHYS_PCI_IO_BASE (max 16M) + * fee00000 60000000 PCI IO PHYS_PCI_IO_BASE (max 16M) * ef000000 Cache flush * f1000000 10000000 Core module registers * f1100000 11000000 System controller registers @@ -147,11 +148,6 @@ static struct map_desc ap_io_desc[] __initdata = { .pfn = __phys_to_pfn(PHYS_PCI_V3_BASE), .length = SZ_64K, .type = MT_DEVICE - }, { - .virtual = PCI_IO_VADDR, - .pfn = __phys_to_pfn(PHYS_PCI_IO_BASE), - .length = SZ_64K, - .type = MT_DEVICE } }; @@ -159,6 +155,7 @@ static void __init ap_map_io(void) { iotable_init(ap_io_desc, ARRAY_SIZE(ap_io_desc)); vga_base = PCI_MEMORY_VADDR; + pci_map_io_early(__phys_to_pfn(PHYS_PCI_IO_BASE)); } #define INTEGRATOR_SC_VALID_INT 0x003fffff diff --git a/arch/arm/mach-integrator/pci_v3.c b/arch/arm/mach-integrator/pci_v3.c index b866880e82ac..495f181fc937 100644 --- a/arch/arm/mach-integrator/pci_v3.c +++ b/arch/arm/mach-integrator/pci_v3.c @@ -41,61 +41,61 @@ /* * The V3 PCI interface chip in Integrator provides several windows from * local bus memory into the PCI memory areas. Unfortunately, there - * are not really enough windows for our usage, therefore we reuse + * are not really enough windows for our usage, therefore we reuse * one of the windows for access to PCI configuration space. The * memory map is as follows: - * + * * Local Bus Memory Usage - * + * * 40000000 - 4FFFFFFF PCI memory. 256M non-prefetchable * 50000000 - 5FFFFFFF PCI memory. 256M prefetchable * 60000000 - 60FFFFFF PCI IO. 16M * 61000000 - 61FFFFFF PCI Configuration. 16M - * + * * There are three V3 windows, each described by a pair of V3 registers. * These are LB_BASE0/LB_MAP0, LB_BASE1/LB_MAP1 and LB_BASE2/LB_MAP2. * Base0 and Base1 can be used for any type of PCI memory access. Base2 * can be used either for PCI I/O or for I20 accesses. By default, uHAL * uses this only for PCI IO space. - * + * * Normally these spaces are mapped using the following base registers: - * + * * Usage Local Bus Memory Base/Map registers used - * + * * Mem 40000000 - 4FFFFFFF LB_BASE0/LB_MAP0 * Mem 50000000 - 5FFFFFFF LB_BASE1/LB_MAP1 * IO 60000000 - 60FFFFFF LB_BASE2/LB_MAP2 * Cfg 61000000 - 61FFFFFF - * + * * This means that I20 and PCI configuration space accesses will fail. - * When PCI configuration accesses are needed (via the uHAL PCI + * When PCI configuration accesses are needed (via the uHAL PCI * configuration space primitives) we must remap the spaces as follows: - * + * * Usage Local Bus Memory Base/Map registers used - * + * * Mem 40000000 - 4FFFFFFF LB_BASE0/LB_MAP0 * Mem 50000000 - 5FFFFFFF LB_BASE0/LB_MAP0 * IO 60000000 - 60FFFFFF LB_BASE2/LB_MAP2 * Cfg 61000000 - 61FFFFFF LB_BASE1/LB_MAP1 - * + * * To make this work, the code depends on overlapping windows working. - * The V3 chip translates an address by checking its range within + * The V3 chip translates an address by checking its range within * each of the BASE/MAP pairs in turn (in ascending register number * order). It will use the first matching pair. So, for example, * if the same address is mapped by both LB_BASE0/LB_MAP0 and - * LB_BASE1/LB_MAP1, the V3 will use the translation from + * LB_BASE1/LB_MAP1, the V3 will use the translation from * LB_BASE0/LB_MAP0. - * + * * To allow PCI Configuration space access, the code enlarges the * window mapped by LB_BASE0/LB_MAP0 from 256M to 512M. This occludes * the windows currently mapped by LB_BASE1/LB_MAP1 so that it can * be remapped for use by configuration cycles. - * - * At the end of the PCI Configuration space accesses, + * + * At the end of the PCI Configuration space accesses, * LB_BASE1/LB_MAP1 is reset to map PCI Memory. Finally the window * mapped by LB_BASE0/LB_MAP0 is reduced in size from 512M to 256M to * reveal the now restored LB_BASE1/LB_MAP1 window. - * + * * NOTE: We do not set up I2O mapping. I suspect that this is only * for an intelligent (target) device. Using I2O disables most of * the mappings into PCI memory. @@ -127,8 +127,8 @@ * * returns: configuration address to play on the PCI bus * - * To generate the appropriate PCI configuration cycles in the PCI - * configuration address space, you present the V3 with the following pattern + * To generate the appropriate PCI configuration cycles in the PCI + * configuration address space, you present the V3 with the following pattern * (which is very nearly a type 1 (except that the lower two bits are 00 and * not 01). In order for this mapping to work you need to set up one of * the local to PCI aperatures to 16Mbytes in length translating to @@ -138,7 +138,7 @@ * * Type 0: * - * 3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1 + * 3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1 * 3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ * | | |D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|F|F|F|R|R|R|R|R|R|0|0| @@ -150,7 +150,7 @@ * * Type 1: * - * 3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1 + * 3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1 * 3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ * | | | | | | | | | | |B|B|B|B|B|B|B|B|D|D|D|D|D|F|F|F|R|R|R|R|R|R|0|1| @@ -161,7 +161,7 @@ * 15:11 Device number (5 bits) * 10:8 function number * 7:2 register number - * + * */ static DEFINE_RAW_SPINLOCK(v3_lock); @@ -374,12 +374,9 @@ static int __init pci_v3_setup_resources(struct pci_sys_data *sys) } /* - * the IO resource for this bus * the mem resource for this bus * the prefetch mem resource for this bus */ - pci_add_resource_offset(&sys->resources, - &ioport_resource, sys->io_offset); pci_add_resource_offset(&sys->resources, &non_mem, sys->mem_offset); pci_add_resource_offset(&sys->resources, &pre_mem, sys->mem_offset); @@ -498,7 +495,6 @@ void __init pci_v3_preinit(void) unsigned int temp; int ret; - pcibios_min_io = 0x6000; pcibios_min_mem = 0x00100000; /* diff --git a/arch/arm/mach-iop13xx/include/mach/io.h b/arch/arm/mach-iop13xx/include/mach/io.h deleted file mode 100644 index f13188518025..000000000000 --- a/arch/arm/mach-iop13xx/include/mach/io.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * iop13xx custom ioremap implementation - * Copyright (c) 2005-2006, Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., 59 Temple - * Place - Suite 330, Boston, MA 02111-1307 USA. - * - */ -#ifndef __ASM_ARM_ARCH_IO_H -#define __ASM_ARM_ARCH_IO_H - -#define IO_SPACE_LIMIT 0xffffffff - -#define __io(a) __iop13xx_io(a) - -extern void __iomem * __iop13xx_io(unsigned long io_addr); - -#endif diff --git a/arch/arm/mach-iop13xx/include/mach/iop13xx.h b/arch/arm/mach-iop13xx/include/mach/iop13xx.h index e190dcd7d72d..e10e101645dd 100644 --- a/arch/arm/mach-iop13xx/include/mach/iop13xx.h +++ b/arch/arm/mach-iop13xx/include/mach/iop13xx.h @@ -69,21 +69,11 @@ extern unsigned long get_iop_tick_rate(void); * 0x8000.0000 + 928M 0x2.8000.0000 (ioremap) PCIE outbound memory window * * IO MAP - * 0x1000 + 64K 0x0.fffb.1000 0xfec6.1000 PCIX outbound i/o window - * 0x1000 + 64K 0x0.fffd.1000 0xfed7.1000 PCIE outbound i/o window + * 0x00000 + 64K 0x0.fffb.0000 0xfee0.0000 PCIX outbound i/o window + * 0x10000 + 64K 0x0.fffd.0000 0xfee1.0000 PCIE outbound i/o window */ -#define IOP13XX_PCIX_IO_WINDOW_SIZE 0x10000UL #define IOP13XX_PCIX_LOWER_IO_PA 0xfffb0000UL -#define IOP13XX_PCIX_LOWER_IO_VA 0xfec60000UL #define IOP13XX_PCIX_LOWER_IO_BA 0x0UL /* OIOTVR */ -#define IOP13XX_PCIX_IO_BUS_OFFSET 0x1000UL -#define IOP13XX_PCIX_UPPER_IO_PA (IOP13XX_PCIX_LOWER_IO_PA +\ - IOP13XX_PCIX_IO_WINDOW_SIZE - 1) -#define IOP13XX_PCIX_UPPER_IO_VA (IOP13XX_PCIX_LOWER_IO_VA +\ - IOP13XX_PCIX_IO_WINDOW_SIZE - 1) -#define IOP13XX_PCIX_IO_PHYS_TO_VIRT(addr) (u32) ((u32) addr -\ - (IOP13XX_PCIX_LOWER_IO_PA\ - - IOP13XX_PCIX_LOWER_IO_VA)) #define IOP13XX_PCIX_MEM_PHYS_OFFSET 0x100000000ULL #define IOP13XX_PCIX_MEM_WINDOW_SIZE 0x3a000000UL @@ -103,20 +93,8 @@ extern unsigned long get_iop_tick_rate(void); IOP13XX_PCIX_LOWER_MEM_BA) /* PCI-E ranges */ -#define IOP13XX_PCIE_IO_WINDOW_SIZE 0x10000UL #define IOP13XX_PCIE_LOWER_IO_PA 0xfffd0000UL -#define IOP13XX_PCIE_LOWER_IO_VA 0xfed70000UL -#define IOP13XX_PCIE_LOWER_IO_BA 0x0UL /* OIOTVR */ -#define IOP13XX_PCIE_IO_BUS_OFFSET 0x1000UL -#define IOP13XX_PCIE_UPPER_IO_PA (IOP13XX_PCIE_LOWER_IO_PA +\ - IOP13XX_PCIE_IO_WINDOW_SIZE - 1) -#define IOP13XX_PCIE_UPPER_IO_VA (IOP13XX_PCIE_LOWER_IO_VA +\ - IOP13XX_PCIE_IO_WINDOW_SIZE - 1) -#define IOP13XX_PCIE_UPPER_IO_BA (IOP13XX_PCIE_LOWER_IO_BA +\ - IOP13XX_PCIE_IO_WINDOW_SIZE - 1) -#define IOP13XX_PCIE_IO_PHYS_TO_VIRT(addr) (u32) ((u32) addr -\ - (IOP13XX_PCIE_LOWER_IO_PA\ - - IOP13XX_PCIE_LOWER_IO_VA)) +#define IOP13XX_PCIE_LOWER_IO_BA 0x10000UL /* OIOTVR */ #define IOP13XX_PCIE_MEM_PHYS_OFFSET 0x200000000ULL #define IOP13XX_PCIE_MEM_WINDOW_SIZE 0x3a000000UL diff --git a/arch/arm/mach-iop13xx/io.c b/arch/arm/mach-iop13xx/io.c index 3c364198db9c..851dc8f2b6b5 100644 --- a/arch/arm/mach-iop13xx/io.c +++ b/arch/arm/mach-iop13xx/io.c @@ -23,25 +23,6 @@ #include "pci.h" -void * __iomem __iop13xx_io(unsigned long io_addr) -{ - void __iomem * io_virt; - - switch (io_addr) { - case IOP13XX_PCIE_LOWER_IO_PA ... IOP13XX_PCIE_UPPER_IO_PA: - io_virt = (void *) IOP13XX_PCIE_IO_PHYS_TO_VIRT(io_addr); - break; - case IOP13XX_PCIX_LOWER_IO_PA ... IOP13XX_PCIX_UPPER_IO_PA: - io_virt = (void *) IOP13XX_PCIX_IO_PHYS_TO_VIRT(io_addr); - break; - default: - BUG(); - } - - return io_virt; -} -EXPORT_SYMBOL(__iop13xx_io); - static void __iomem *__iop13xx_ioremap_caller(unsigned long cookie, size_t size, unsigned int mtype, void *caller) { @@ -67,12 +48,6 @@ static void __iomem *__iop13xx_ioremap_caller(unsigned long cookie, (cookie - IOP13XX_PBI_LOWER_MEM_RA), size, mtype, __builtin_return_address(0)); break; - case IOP13XX_PCIE_LOWER_IO_PA ... IOP13XX_PCIE_UPPER_IO_PA: - retval = (void *) IOP13XX_PCIE_IO_PHYS_TO_VIRT(cookie); - break; - case IOP13XX_PCIX_LOWER_IO_PA ... IOP13XX_PCIX_UPPER_IO_PA: - retval = (void *) IOP13XX_PCIX_IO_PHYS_TO_VIRT(cookie); - break; case IOP13XX_PMMR_PHYS_MEM_BASE ... IOP13XX_PMMR_UPPER_MEM_PA: retval = (void *) IOP13XX_PMMR_PHYS_TO_VIRT(cookie); break; @@ -99,8 +74,6 @@ static void __iop13xx_iounmap(volatile void __iomem *addr) goto skip; switch ((u32) addr) { - case IOP13XX_PCIE_LOWER_IO_VA ... IOP13XX_PCIE_UPPER_IO_VA: - case IOP13XX_PCIX_LOWER_IO_VA ... IOP13XX_PCIX_UPPER_IO_VA: case IOP13XX_PMMR_VIRT_MEM_BASE ... IOP13XX_PMMR_UPPER_MEM_VA: goto skip; } diff --git a/arch/arm/mach-iop13xx/pci.c b/arch/arm/mach-iop13xx/pci.c index 861cb12ef436..91f731a2957b 100644 --- a/arch/arm/mach-iop13xx/pci.c +++ b/arch/arm/mach-iop13xx/pci.c @@ -970,7 +970,6 @@ void __init iop13xx_pci_init(void) __raw_writel(__raw_readl(IOP13XX_XBG_BECSR) & 3, IOP13XX_XBG_BECSR); /* Setup the Min Address for PCI memory... */ - pcibios_min_io = 0; pcibios_min_mem = IOP13XX_PCIX_LOWER_MEM_BA; /* if Linux is given control of an ATU @@ -1003,7 +1002,7 @@ int iop13xx_pci_setup(int nr, struct pci_sys_data *sys) if (nr > 1) return 0; - res = kcalloc(2, sizeof(struct resource), GFP_KERNEL); + res = kzalloc(sizeof(struct resource), GFP_KERNEL); if (!res) panic("PCI: unable to alloc resources"); @@ -1042,17 +1041,13 @@ int iop13xx_pci_setup(int nr, struct pci_sys_data *sys) << IOP13XX_ATUX_PCIXSR_FUNC_NUM; __raw_writel(pcixsr, IOP13XX_ATUX_PCIXSR); - res[0].start = IOP13XX_PCIX_LOWER_IO_PA + IOP13XX_PCIX_IO_BUS_OFFSET; - res[0].end = IOP13XX_PCIX_UPPER_IO_PA; - res[0].name = "IQ81340 ATUX PCI I/O Space"; - res[0].flags = IORESOURCE_IO; + pci_ioremap_io(0, IOP13XX_PCIX_LOWER_IO_PA); - res[1].start = IOP13XX_PCIX_LOWER_MEM_RA; - res[1].end = IOP13XX_PCIX_UPPER_MEM_RA; - res[1].name = "IQ81340 ATUX PCI Memory Space"; - res[1].flags = IORESOURCE_MEM; + res->start = IOP13XX_PCIX_LOWER_MEM_RA; + res->end = IOP13XX_PCIX_UPPER_MEM_RA; + res->name = "IQ81340 ATUX PCI Memory Space"; + res->flags = IORESOURCE_MEM; sys->mem_offset = IOP13XX_PCIX_MEM_OFFSET; - sys->io_offset = IOP13XX_PCIX_LOWER_IO_PA; break; case IOP13XX_INIT_ATU_ATUE: /* Note: the function number field in the PCSR is ro */ @@ -1063,17 +1058,13 @@ int iop13xx_pci_setup(int nr, struct pci_sys_data *sys) __raw_writel(pcsr, IOP13XX_ATUE_PCSR); - res[0].start = IOP13XX_PCIE_LOWER_IO_PA + IOP13XX_PCIE_IO_BUS_OFFSET; - res[0].end = IOP13XX_PCIE_UPPER_IO_PA; - res[0].name = "IQ81340 ATUE PCI I/O Space"; - res[0].flags = IORESOURCE_IO; + pci_ioremap_io(SZ_64K, IOP13XX_PCIE_LOWER_IO_PA); - res[1].start = IOP13XX_PCIE_LOWER_MEM_RA; - res[1].end = IOP13XX_PCIE_UPPER_MEM_RA; - res[1].name = "IQ81340 ATUE PCI Memory Space"; - res[1].flags = IORESOURCE_MEM; + res->start = IOP13XX_PCIE_LOWER_MEM_RA; + res->end = IOP13XX_PCIE_UPPER_MEM_RA; + res->name = "IQ81340 ATUE PCI Memory Space"; + res->flags = IORESOURCE_MEM; sys->mem_offset = IOP13XX_PCIE_MEM_OFFSET; - sys->io_offset = IOP13XX_PCIE_LOWER_IO_PA; sys->map_irq = iop13xx_pcie_map_irq; break; default: @@ -1081,11 +1072,9 @@ int iop13xx_pci_setup(int nr, struct pci_sys_data *sys) return 0; } - request_resource(&ioport_resource, &res[0]); - request_resource(&iomem_resource, &res[1]); + request_resource(&iomem_resource, res); - pci_add_resource_offset(&sys->resources, &res[0], sys->io_offset); - pci_add_resource_offset(&sys->resources, &res[1], sys->mem_offset); + pci_add_resource_offset(&sys->resources, res, sys->mem_offset); return 1; } diff --git a/arch/arm/mach-iop13xx/setup.c b/arch/arm/mach-iop13xx/setup.c index daabb1fa6c2c..4a7f20d7fb6e 100644 --- a/arch/arm/mach-iop13xx/setup.c +++ b/arch/arm/mach-iop13xx/setup.c @@ -40,16 +40,6 @@ static struct map_desc iop13xx_std_desc[] __initdata = { .pfn = __phys_to_pfn(IOP13XX_PMMR_PHYS_MEM_BASE), .length = IOP13XX_PMMR_SIZE, .type = MT_DEVICE, - }, { /* PCIE IO space */ - .virtual = IOP13XX_PCIE_LOWER_IO_VA, - .pfn = __phys_to_pfn(IOP13XX_PCIE_LOWER_IO_PA), - .length = IOP13XX_PCIX_IO_WINDOW_SIZE, - .type = MT_DEVICE, - }, { /* PCIX IO space */ - .virtual = IOP13XX_PCIX_LOWER_IO_VA, - .pfn = __phys_to_pfn(IOP13XX_PCIX_LOWER_IO_PA), - .length = IOP13XX_PCIX_IO_WINDOW_SIZE, - .type = MT_DEVICE, }, }; diff --git a/arch/arm/mach-iop32x/include/mach/io.h b/arch/arm/mach-iop32x/include/mach/io.h deleted file mode 100644 index e2ada265bb8d..000000000000 --- a/arch/arm/mach-iop32x/include/mach/io.h +++ /dev/null @@ -1,19 +0,0 @@ -/* - * arch/arm/mach-iop32x/include/mach/io.h - * - * Copyright (C) 2001 MontaVista Software, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __IO_H -#define __IO_H - -#include <asm/hardware/iop3xx.h> - -#define IO_SPACE_LIMIT 0xffffffff -#define __io(p) ((void __iomem *)IOP3XX_PCI_IO_PHYS_TO_VIRT(p)) - -#endif diff --git a/arch/arm/mach-iop33x/include/mach/io.h b/arch/arm/mach-iop33x/include/mach/io.h deleted file mode 100644 index f7c1b6595660..000000000000 --- a/arch/arm/mach-iop33x/include/mach/io.h +++ /dev/null @@ -1,19 +0,0 @@ -/* - * arch/arm/mach-iop33x/include/mach/io.h - * - * Copyright (C) 2001 MontaVista Software, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __IO_H -#define __IO_H - -#include <asm/hardware/iop3xx.h> - -#define IO_SPACE_LIMIT 0xffffffff -#define __io(p) ((void __iomem *)IOP3XX_PCI_IO_PHYS_TO_VIRT(p)) - -#endif diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c index c4b64adcbfce..31d9f400ed82 100644 --- a/arch/arm/mach-kirkwood/common.c +++ b/arch/arm/mach-kirkwood/common.c @@ -42,16 +42,6 @@ ****************************************************************************/ static struct map_desc kirkwood_io_desc[] __initdata = { { - .virtual = KIRKWOOD_PCIE_IO_VIRT_BASE, - .pfn = __phys_to_pfn(KIRKWOOD_PCIE_IO_PHYS_BASE), - .length = KIRKWOOD_PCIE_IO_SIZE, - .type = MT_DEVICE, - }, { - .virtual = KIRKWOOD_PCIE1_IO_VIRT_BASE, - .pfn = __phys_to_pfn(KIRKWOOD_PCIE1_IO_PHYS_BASE), - .length = KIRKWOOD_PCIE1_IO_SIZE, - .type = MT_DEVICE, - }, { .virtual = KIRKWOOD_REGS_VIRT_BASE, .pfn = __phys_to_pfn(KIRKWOOD_REGS_PHYS_BASE), .length = KIRKWOOD_REGS_SIZE, diff --git a/arch/arm/mach-kirkwood/include/mach/io.h b/arch/arm/mach-kirkwood/include/mach/io.h deleted file mode 100644 index 5d0ab61700d2..000000000000 --- a/arch/arm/mach-kirkwood/include/mach/io.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * arch/arm/mach-kirkwood/include/mach/io.h - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef __ASM_ARCH_IO_H -#define __ASM_ARCH_IO_H - -#include "kirkwood.h" - -#define IO_SPACE_LIMIT 0xffffffff - -static inline void __iomem *__io(unsigned long addr) -{ - return (void __iomem *)((addr - KIRKWOOD_PCIE_IO_BUS_BASE) - + KIRKWOOD_PCIE_IO_VIRT_BASE); -} - -#define __io(a) __io(a) - -#endif diff --git a/arch/arm/mach-kirkwood/include/mach/kirkwood.h b/arch/arm/mach-kirkwood/include/mach/kirkwood.h index c5b68510776b..af4f0000dcef 100644 --- a/arch/arm/mach-kirkwood/include/mach/kirkwood.h +++ b/arch/arm/mach-kirkwood/include/mach/kirkwood.h @@ -37,14 +37,12 @@ #define KIRKWOOD_NAND_MEM_SIZE SZ_1K #define KIRKWOOD_PCIE1_IO_PHYS_BASE 0xf3000000 -#define KIRKWOOD_PCIE1_IO_VIRT_BASE 0xfef00000 -#define KIRKWOOD_PCIE1_IO_BUS_BASE 0x00100000 -#define KIRKWOOD_PCIE1_IO_SIZE SZ_1M +#define KIRKWOOD_PCIE1_IO_BUS_BASE 0x00010000 +#define KIRKWOOD_PCIE1_IO_SIZE SZ_64K #define KIRKWOOD_PCIE_IO_PHYS_BASE 0xf2000000 -#define KIRKWOOD_PCIE_IO_VIRT_BASE 0xfee00000 #define KIRKWOOD_PCIE_IO_BUS_BASE 0x00000000 -#define KIRKWOOD_PCIE_IO_SIZE SZ_1M +#define KIRKWOOD_PCIE_IO_SIZE SZ_64K #define KIRKWOOD_REGS_PHYS_BASE 0xf1000000 #define KIRKWOOD_REGS_VIRT_BASE 0xfed00000 diff --git a/arch/arm/mach-kirkwood/pcie.c b/arch/arm/mach-kirkwood/pcie.c index 6e8b2efa3c35..532d8acb38f9 100644 --- a/arch/arm/mach-kirkwood/pcie.c +++ b/arch/arm/mach-kirkwood/pcie.c @@ -56,7 +56,7 @@ struct pcie_port { void __iomem *base; spinlock_t conf_lock; int irq; - struct resource res[2]; + struct resource res; }; static int pcie_port_map[2]; @@ -137,20 +137,12 @@ static void __init pcie0_ioresources_init(struct pcie_port *pp) pp->irq = IRQ_KIRKWOOD_PCIE; /* - * IORESOURCE_IO - */ - pp->res[0].name = "PCIe 0 I/O Space"; - pp->res[0].start = KIRKWOOD_PCIE_IO_BUS_BASE; - pp->res[0].end = pp->res[0].start + KIRKWOOD_PCIE_IO_SIZE - 1; - pp->res[0].flags = IORESOURCE_IO; - - /* * IORESOURCE_MEM */ - pp->res[1].name = "PCIe 0 MEM"; - pp->res[1].start = KIRKWOOD_PCIE_MEM_PHYS_BASE; - pp->res[1].end = pp->res[1].start + KIRKWOOD_PCIE_MEM_SIZE - 1; - pp->res[1].flags = IORESOURCE_MEM; + pp->res.name = "PCIe 0 MEM"; + pp->res.start = KIRKWOOD_PCIE_MEM_PHYS_BASE; + pp->res.end = pp->res.start + KIRKWOOD_PCIE_MEM_SIZE - 1; + pp->res.flags = IORESOURCE_MEM; } static void __init pcie1_ioresources_init(struct pcie_port *pp) @@ -159,20 +151,12 @@ static void __init pcie1_ioresources_init(struct pcie_port *pp) pp->irq = IRQ_KIRKWOOD_PCIE1; /* - * IORESOURCE_IO - */ - pp->res[0].name = "PCIe 1 I/O Space"; - pp->res[0].start = KIRKWOOD_PCIE1_IO_BUS_BASE; - pp->res[0].end = pp->res[0].start + KIRKWOOD_PCIE1_IO_SIZE - 1; - pp->res[0].flags = IORESOURCE_IO; - - /* * IORESOURCE_MEM */ - pp->res[1].name = "PCIe 1 MEM"; - pp->res[1].start = KIRKWOOD_PCIE1_MEM_PHYS_BASE; - pp->res[1].end = pp->res[1].start + KIRKWOOD_PCIE1_MEM_SIZE - 1; - pp->res[1].flags = IORESOURCE_MEM; + pp->res.name = "PCIe 1 MEM"; + pp->res.start = KIRKWOOD_PCIE1_MEM_PHYS_BASE; + pp->res.end = pp->res.start + KIRKWOOD_PCIE1_MEM_SIZE - 1; + pp->res.flags = IORESOURCE_MEM; } static int __init kirkwood_pcie_setup(int nr, struct pci_sys_data *sys) @@ -197,23 +181,21 @@ static int __init kirkwood_pcie_setup(int nr, struct pci_sys_data *sys) case 0: kirkwood_enable_pcie_clk("0"); pcie0_ioresources_init(pp); + pci_ioremap_io(SZ_64K * sys->busnr, KIRKWOOD_PCIE_IO_PHYS_BASE); break; case 1: kirkwood_enable_pcie_clk("1"); pcie1_ioresources_init(pp); + pci_ioremap_io(SZ_64K * sys->busnr, KIRKWOOD_PCIE1_IO_PHYS_BASE); break; default: panic("PCIe setup: invalid controller %d", index); } - if (request_resource(&ioport_resource, &pp->res[0])) - panic("Request PCIe%d IO resource failed\n", index); - if (request_resource(&iomem_resource, &pp->res[1])) + if (request_resource(&iomem_resource, &pp->res)) panic("Request PCIe%d Memory resource failed\n", index); - sys->io_offset = 0; - pci_add_resource_offset(&sys->resources, &pp->res[0], sys->io_offset); - pci_add_resource_offset(&sys->resources, &pp->res[1], sys->mem_offset); + pci_add_resource_offset(&sys->resources, &pp->res, sys->mem_offset); /* * Generic PCIe unit setup. diff --git a/arch/arm/mach-mv78xx0/addr-map.c b/arch/arm/mach-mv78xx0/addr-map.c index 62b53d710efd..7764d9386f2a 100644 --- a/arch/arm/mach-mv78xx0/addr-map.c +++ b/arch/arm/mach-mv78xx0/addr-map.c @@ -13,6 +13,7 @@ #include <linux/mbus.h> #include <linux/io.h> #include <plat/addr-map.h> +#include <mach/mv78xx0.h> #include "common.h" /* @@ -81,7 +82,7 @@ void __init mv78xx0_setup_pcie_io_win(int window, u32 base, u32 size, int maj, int min) { orion_setup_cpu_win(&addr_map_cfg, window, base, size, - TARGET_PCIE(maj), ATTR_PCIE_IO(min), -1); + TARGET_PCIE(maj), ATTR_PCIE_IO(min), 0); } void __init mv78xx0_setup_pcie_mem_win(int window, u32 base, u32 size, diff --git a/arch/arm/mach-mv78xx0/common.c b/arch/arm/mach-mv78xx0/common.c index b4c53b846c9c..20826449e61b 100644 --- a/arch/arm/mach-mv78xx0/common.c +++ b/arch/arm/mach-mv78xx0/common.c @@ -135,11 +135,6 @@ static struct map_desc mv78xx0_io_desc[] __initdata = { .length = MV78XX0_CORE_REGS_SIZE, .type = MT_DEVICE, }, { - .virtual = MV78XX0_PCIE_IO_VIRT_BASE(0), - .pfn = __phys_to_pfn(MV78XX0_PCIE_IO_PHYS_BASE(0)), - .length = MV78XX0_PCIE_IO_SIZE * 8, - .type = MT_DEVICE, - }, { .virtual = MV78XX0_REGS_VIRT_BASE, .pfn = __phys_to_pfn(MV78XX0_REGS_PHYS_BASE), .length = MV78XX0_REGS_SIZE, diff --git a/arch/arm/mach-mv78xx0/include/mach/io.h b/arch/arm/mach-mv78xx0/include/mach/io.h deleted file mode 100644 index c7d9d00d8fc1..000000000000 --- a/arch/arm/mach-mv78xx0/include/mach/io.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * arch/arm/mach-mv78xx0/include/mach/io.h - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef __ASM_ARCH_IO_H -#define __ASM_ARCH_IO_H - -#include "mv78xx0.h" - -#define IO_SPACE_LIMIT 0xffffffff - -static inline void __iomem *__io(unsigned long addr) -{ - return (void __iomem *)((addr - MV78XX0_PCIE_IO_PHYS_BASE(0)) - + MV78XX0_PCIE_IO_VIRT_BASE(0)); -} - -#define __io(a) __io(a) - -#endif diff --git a/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h b/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h index e807c4c52a0b..bd03fed1128e 100644 --- a/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h +++ b/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h @@ -29,15 +29,15 @@ * * virt phys size * fe400000 f102x000 16K core-specific peripheral registers - * fe700000 f0800000 1M PCIe #0 I/O space - * fe800000 f0900000 1M PCIe #1 I/O space - * fe900000 f0a00000 1M PCIe #2 I/O space - * fea00000 f0b00000 1M PCIe #3 I/O space - * feb00000 f0c00000 1M PCIe #4 I/O space - * fec00000 f0d00000 1M PCIe #5 I/O space - * fed00000 f0e00000 1M PCIe #6 I/O space - * fee00000 f0f00000 1M PCIe #7 I/O space - * fef00000 f1000000 1M on-chip peripheral registers + * fee00000 f0800000 64K PCIe #0 I/O space + * fee10000 f0900000 64K PCIe #1 I/O space + * fee20000 f0a00000 64K PCIe #2 I/O space + * fee30000 f0b00000 64K PCIe #3 I/O space + * fee40000 f0c00000 64K PCIe #4 I/O space + * fee50000 f0d00000 64K PCIe #5 I/O space + * fee60000 f0e00000 64K PCIe #6 I/O space + * fee70000 f0f00000 64K PCIe #7 I/O space + * fd000000 f1000000 1M on-chip peripheral registers */ #define MV78XX0_CORE0_REGS_PHYS_BASE 0xf1020000 #define MV78XX0_CORE1_REGS_PHYS_BASE 0xf1024000 @@ -46,11 +46,10 @@ #define MV78XX0_CORE_REGS_SIZE SZ_16K #define MV78XX0_PCIE_IO_PHYS_BASE(i) (0xf0800000 + ((i) << 20)) -#define MV78XX0_PCIE_IO_VIRT_BASE(i) (0xfe700000 + ((i) << 20)) #define MV78XX0_PCIE_IO_SIZE SZ_1M #define MV78XX0_REGS_PHYS_BASE 0xf1000000 -#define MV78XX0_REGS_VIRT_BASE 0xfef00000 +#define MV78XX0_REGS_VIRT_BASE 0xfd000000 #define MV78XX0_REGS_SIZE SZ_1M #define MV78XX0_PCIE_MEM_PHYS_BASE 0xc0000000 diff --git a/arch/arm/mach-mv78xx0/pcie.c b/arch/arm/mach-mv78xx0/pcie.c index 2e56e86b6d68..26a059b4f472 100644 --- a/arch/arm/mach-mv78xx0/pcie.c +++ b/arch/arm/mach-mv78xx0/pcie.c @@ -15,6 +15,7 @@ #include <asm/mach/pci.h> #include <plat/pcie.h> #include <plat/addr-map.h> +#include <mach/mv78xx0.h> #include "common.h" struct pcie_port { @@ -23,16 +24,13 @@ struct pcie_port { u8 root_bus_nr; void __iomem *base; spinlock_t conf_lock; - char io_space_name[16]; char mem_space_name[16]; - struct resource res[2]; + struct resource res; }; static struct pcie_port pcie_port[8]; static int num_pcie_ports; static struct resource pcie_io_space; -static struct resource pcie_mem_space; - void __init mv78xx0_pcie_id(u32 *dev, u32 *rev) { @@ -40,102 +38,59 @@ void __init mv78xx0_pcie_id(u32 *dev, u32 *rev) *rev = orion_pcie_rev((void __iomem *)PCIE00_VIRT_BASE); } +u32 pcie_port_size[8] = { + 0, + 0x30000000, + 0x10000000, + 0x10000000, + 0x08000000, + 0x08000000, + 0x08000000, + 0x04000000, +}; + static void __init mv78xx0_pcie_preinit(void) { int i; u32 size_each; u32 start; - int win; + int win = 0; pcie_io_space.name = "PCIe I/O Space"; pcie_io_space.start = MV78XX0_PCIE_IO_PHYS_BASE(0); pcie_io_space.end = MV78XX0_PCIE_IO_PHYS_BASE(0) + MV78XX0_PCIE_IO_SIZE * 8 - 1; - pcie_io_space.flags = IORESOURCE_IO; + pcie_io_space.flags = IORESOURCE_MEM; if (request_resource(&iomem_resource, &pcie_io_space)) panic("can't allocate PCIe I/O space"); - pcie_mem_space.name = "PCIe MEM Space"; - pcie_mem_space.start = MV78XX0_PCIE_MEM_PHYS_BASE; - pcie_mem_space.end = - MV78XX0_PCIE_MEM_PHYS_BASE + MV78XX0_PCIE_MEM_SIZE - 1; - pcie_mem_space.flags = IORESOURCE_MEM; - if (request_resource(&iomem_resource, &pcie_mem_space)) - panic("can't allocate PCIe MEM space"); + if (num_pcie_ports > 7) + panic("invalid number of PCIe ports"); + + size_each = pcie_port_size[num_pcie_ports]; + start = MV78XX0_PCIE_MEM_PHYS_BASE; for (i = 0; i < num_pcie_ports; i++) { struct pcie_port *pp = pcie_port + i; - snprintf(pp->io_space_name, sizeof(pp->io_space_name), - "PCIe %d.%d I/O", pp->maj, pp->min); - pp->io_space_name[sizeof(pp->io_space_name) - 1] = 0; - pp->res[0].name = pp->io_space_name; - pp->res[0].start = MV78XX0_PCIE_IO_PHYS_BASE(i); - pp->res[0].end = pp->res[0].start + MV78XX0_PCIE_IO_SIZE - 1; - pp->res[0].flags = IORESOURCE_IO; - snprintf(pp->mem_space_name, sizeof(pp->mem_space_name), "PCIe %d.%d MEM", pp->maj, pp->min); pp->mem_space_name[sizeof(pp->mem_space_name) - 1] = 0; - pp->res[1].name = pp->mem_space_name; - pp->res[1].flags = IORESOURCE_MEM; - } - - switch (num_pcie_ports) { - case 0: - size_each = 0; - break; - - case 1: - size_each = 0x30000000; - break; - - case 2 ... 3: - size_each = 0x10000000; - break; - - case 4 ... 6: - size_each = 0x08000000; - break; - - case 7: - size_each = 0x04000000; - break; - - default: - panic("invalid number of PCIe ports"); - } - - start = MV78XX0_PCIE_MEM_PHYS_BASE; - for (i = 0; i < num_pcie_ports; i++) { - struct pcie_port *pp = pcie_port + i; - - pp->res[1].start = start; - pp->res[1].end = start + size_each - 1; + pp->res.name = pp->mem_space_name; + pp->res.flags = IORESOURCE_MEM; + pp->res.start = start; + pp->res.end = start + size_each - 1; start += size_each; - } - - for (i = 0; i < num_pcie_ports; i++) { - struct pcie_port *pp = pcie_port + i; - if (request_resource(&pcie_io_space, &pp->res[0])) - panic("can't allocate PCIe I/O sub-space"); - - if (request_resource(&pcie_mem_space, &pp->res[1])) + if (request_resource(&iomem_resource, &pp->res)) panic("can't allocate PCIe MEM sub-space"); - } - win = 0; - for (i = 0; i < num_pcie_ports; i++) { - struct pcie_port *pp = pcie_port + i; + mv78xx0_setup_pcie_mem_win(win + i + 8, pp->res.start, + resource_size(&pp->res), + pp->maj, pp->min); - mv78xx0_setup_pcie_io_win(win++, pp->res[0].start, - resource_size(&pp->res[0]), + mv78xx0_setup_pcie_io_win(win + i, i * SZ_64K, SZ_64K, pp->maj, pp->min); - - mv78xx0_setup_pcie_mem_win(win++, pp->res[1].start, - resource_size(&pp->res[1]), - pp->maj, pp->min); } } @@ -156,8 +111,9 @@ static int __init mv78xx0_pcie_setup(int nr, struct pci_sys_data *sys) orion_pcie_set_local_bus_nr(pp->base, sys->busnr); orion_pcie_setup(pp->base); - pci_add_resource_offset(&sys->resources, &pp->res[0], sys->io_offset); - pci_add_resource_offset(&sys->resources, &pp->res[1], sys->mem_offset); + pci_ioremap_io(nr * SZ_64K, MV78XX0_PCIE_IO_PHYS_BASE(nr)); + + pci_add_resource_offset(&sys->resources, &pp->res, sys->mem_offset); return 1; } @@ -281,7 +237,7 @@ static void __init add_pcie_port(int maj, int min, unsigned long base) pp->root_bus_nr = -1; pp->base = (void __iomem *)base; spin_lock_init(&pp->conf_lock); - memset(pp->res, 0, sizeof(pp->res)); + memset(&pp->res, 0, sizeof(pp->res)); } else { printk("link down, ignoring\n"); } diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c index 9148b229d0de..70f7d712d6f4 100644 --- a/arch/arm/mach-orion5x/common.c +++ b/arch/arm/mach-orion5x/common.c @@ -47,16 +47,6 @@ static struct map_desc orion5x_io_desc[] __initdata = { .length = ORION5X_REGS_SIZE, .type = MT_DEVICE, }, { - .virtual = ORION5X_PCIE_IO_VIRT_BASE, - .pfn = __phys_to_pfn(ORION5X_PCIE_IO_PHYS_BASE), - .length = ORION5X_PCIE_IO_SIZE, - .type = MT_DEVICE, - }, { - .virtual = ORION5X_PCI_IO_VIRT_BASE, - .pfn = __phys_to_pfn(ORION5X_PCI_IO_PHYS_BASE), - .length = ORION5X_PCI_IO_SIZE, - .type = MT_DEVICE, - }, { .virtual = ORION5X_PCIE_WA_VIRT_BASE, .pfn = __phys_to_pfn(ORION5X_PCIE_WA_PHYS_BASE), .length = ORION5X_PCIE_WA_SIZE, diff --git a/arch/arm/mach-orion5x/include/mach/io.h b/arch/arm/mach-orion5x/include/mach/io.h deleted file mode 100644 index 1aa5d0a50a0b..000000000000 --- a/arch/arm/mach-orion5x/include/mach/io.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * arch/arm/mach-orion5x/include/mach/io.h - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef __ASM_ARCH_IO_H -#define __ASM_ARCH_IO_H - -#include <mach/orion5x.h> -#include <asm/sizes.h> - -#define IO_SPACE_LIMIT SZ_2M -static inline void __iomem *__io(unsigned long addr) -{ - return (void __iomem *)(addr + ORION5X_PCIE_IO_VIRT_BASE); -} - -#define __io(a) __io(a) -#endif diff --git a/arch/arm/mach-orion5x/include/mach/orion5x.h b/arch/arm/mach-orion5x/include/mach/orion5x.h index 683e085ce162..1b60131b7f60 100644 --- a/arch/arm/mach-orion5x/include/mach/orion5x.h +++ b/arch/arm/mach-orion5x/include/mach/orion5x.h @@ -31,31 +31,29 @@ * fc000000 device bus mappings (cs0/cs1) * * virt phys size - * fdd00000 f1000000 1M on-chip peripheral registers - * fde00000 f2000000 1M PCIe I/O space - * fdf00000 f2100000 1M PCI I/O space - * fe000000 f0000000 16M PCIe WA space (Orion-1/Orion-NAS only) + * fe000000 f1000000 1M on-chip peripheral registers + * fee00000 f2000000 64K PCIe I/O space + * fee10000 f2100000 64K PCI I/O space + * fd000000 f0000000 16M PCIe WA space (Orion-1/Orion-NAS only) ****************************************************************************/ #define ORION5X_REGS_PHYS_BASE 0xf1000000 -#define ORION5X_REGS_VIRT_BASE 0xfdd00000 +#define ORION5X_REGS_VIRT_BASE 0xfe000000 #define ORION5X_REGS_SIZE SZ_1M #define ORION5X_PCIE_IO_PHYS_BASE 0xf2000000 -#define ORION5X_PCIE_IO_VIRT_BASE 0xfde00000 #define ORION5X_PCIE_IO_BUS_BASE 0x00000000 -#define ORION5X_PCIE_IO_SIZE SZ_1M +#define ORION5X_PCIE_IO_SIZE SZ_64K #define ORION5X_PCI_IO_PHYS_BASE 0xf2100000 -#define ORION5X_PCI_IO_VIRT_BASE 0xfdf00000 -#define ORION5X_PCI_IO_BUS_BASE 0x00100000 -#define ORION5X_PCI_IO_SIZE SZ_1M +#define ORION5X_PCI_IO_BUS_BASE 0x00010000 +#define ORION5X_PCI_IO_SIZE SZ_64K #define ORION5X_SRAM_PHYS_BASE (0xf2200000) #define ORION5X_SRAM_SIZE SZ_8K /* Relevant only for Orion-1/Orion-NAS */ #define ORION5X_PCIE_WA_PHYS_BASE 0xf0000000 -#define ORION5X_PCIE_WA_VIRT_BASE 0xfe000000 +#define ORION5X_PCIE_WA_VIRT_BASE 0xfd000000 #define ORION5X_PCIE_WA_SIZE SZ_16M #define ORION5X_PCIE_MEM_PHYS_BASE 0xe0000000 diff --git a/arch/arm/mach-orion5x/pci.c b/arch/arm/mach-orion5x/pci.c index cb19e1661bb3..6921d49b988d 100644 --- a/arch/arm/mach-orion5x/pci.c +++ b/arch/arm/mach-orion5x/pci.c @@ -162,35 +162,25 @@ static int __init pcie_setup(struct pci_sys_data *sys) pcie_ops.read = pcie_rd_conf_wa; } + pci_ioremap_io(sys->busnr * SZ_64K, ORION5X_PCIE_IO_PHYS_BASE); + /* * Request resources. */ - res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL); + res = kzalloc(sizeof(struct resource), GFP_KERNEL); if (!res) panic("pcie_setup unable to alloc resources"); /* - * IORESOURCE_IO - */ - sys->io_offset = 0; - res[0].name = "PCIe I/O Space"; - res[0].flags = IORESOURCE_IO; - res[0].start = ORION5X_PCIE_IO_BUS_BASE; - res[0].end = res[0].start + ORION5X_PCIE_IO_SIZE - 1; - if (request_resource(&ioport_resource, &res[0])) - panic("Request PCIe IO resource failed\n"); - pci_add_resource_offset(&sys->resources, &res[0], sys->io_offset); - - /* * IORESOURCE_MEM */ - res[1].name = "PCIe Memory Space"; - res[1].flags = IORESOURCE_MEM; - res[1].start = ORION5X_PCIE_MEM_PHYS_BASE; - res[1].end = res[1].start + ORION5X_PCIE_MEM_SIZE - 1; - if (request_resource(&iomem_resource, &res[1])) + res->name = "PCIe Memory Space"; + res->flags = IORESOURCE_MEM; + res->start = ORION5X_PCIE_MEM_PHYS_BASE; + res->end = res->start + ORION5X_PCIE_MEM_SIZE - 1; + if (request_resource(&iomem_resource, res)) panic("Request PCIe Memory resource failed\n"); - pci_add_resource_offset(&sys->resources, &res[1], sys->mem_offset); + pci_add_resource_offset(&sys->resources, res, sys->mem_offset); return 1; } @@ -489,35 +479,25 @@ static int __init pci_setup(struct pci_sys_data *sys) */ orion5x_setbits(PCI_CMD, PCI_CMD_HOST_REORDER); + pci_ioremap_io(sys->busnr * SZ_64K, ORION5X_PCI_IO_PHYS_BASE); + /* * Request resources */ - res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL); + res = kzalloc(sizeof(struct resource), GFP_KERNEL); if (!res) panic("pci_setup unable to alloc resources"); /* - * IORESOURCE_IO - */ - sys->io_offset = 0; - res[0].name = "PCI I/O Space"; - res[0].flags = IORESOURCE_IO; - res[0].start = ORION5X_PCI_IO_BUS_BASE; - res[0].end = res[0].start + ORION5X_PCI_IO_SIZE - 1; - if (request_resource(&ioport_resource, &res[0])) - panic("Request PCI IO resource failed\n"); - pci_add_resource_offset(&sys->resources, &res[0], sys->io_offset); - - /* * IORESOURCE_MEM */ - res[1].name = "PCI Memory Space"; - res[1].flags = IORESOURCE_MEM; - res[1].start = ORION5X_PCI_MEM_PHYS_BASE; - res[1].end = res[1].start + ORION5X_PCI_MEM_SIZE - 1; - if (request_resource(&iomem_resource, &res[1])) + res->name = "PCI Memory Space"; + res->flags = IORESOURCE_MEM; + res->start = ORION5X_PCI_MEM_PHYS_BASE; + res->end = res->start + ORION5X_PCI_MEM_SIZE - 1; + if (request_resource(&iomem_resource, res)) panic("Request PCI Memory resource failed\n"); - pci_add_resource_offset(&sys->resources, &res[1], sys->mem_offset); + pci_add_resource_offset(&sys->resources, res, sys->mem_offset); return 1; } diff --git a/arch/arm/mach-prima2/Kconfig b/arch/arm/mach-prima2/Kconfig new file mode 100644 index 000000000000..41fc85327673 --- /dev/null +++ b/arch/arm/mach-prima2/Kconfig @@ -0,0 +1,19 @@ +if ARCH_SIRF + +menu "CSR SiRF primaII/Marco/Polo Specific Features" + +config ARCH_PRIMA2 + bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform" + default y + select CPU_V7 + select ZONE_DMA + select SIRF_IRQ + help + Support for CSR SiRFSoC ARM Cortex A9 Platform + +endmenu + +config SIRF_IRQ + bool + +endif diff --git a/arch/arm/mach-prima2/Makefile b/arch/arm/mach-prima2/Makefile index 13dd1604d951..fc9ce22e2b5a 100644 --- a/arch/arm/mach-prima2/Makefile +++ b/arch/arm/mach-prima2/Makefile @@ -1,9 +1,8 @@ obj-y := timer.o -obj-y += irq.o -obj-y += clock.o obj-y += rstc.o -obj-y += prima2.o +obj-y += common.o obj-y += rtciobrg.o obj-$(CONFIG_DEBUG_LL) += lluart.o obj-$(CONFIG_CACHE_L2X0) += l2x0.o obj-$(CONFIG_SUSPEND) += pm.o sleep.o +obj-$(CONFIG_SIRF_IRQ) += irq.o diff --git a/arch/arm/mach-prima2/clock.c b/arch/arm/mach-prima2/clock.c deleted file mode 100644 index aebad7e565cf..000000000000 --- a/arch/arm/mach-prima2/clock.c +++ /dev/null @@ -1,510 +0,0 @@ -/* - * Clock tree for CSR SiRFprimaII - * - * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company. - * - * Licensed under GPLv2 or later. - */ - -#include <linux/module.h> -#include <linux/bitops.h> -#include <linux/err.h> -#include <linux/errno.h> -#include <linux/io.h> -#include <linux/clkdev.h> -#include <linux/clk.h> -#include <linux/spinlock.h> -#include <linux/of.h> -#include <linux/of_address.h> -#include <asm/mach/map.h> -#include <mach/map.h> - -#define SIRFSOC_CLKC_CLK_EN0 0x0000 -#define SIRFSOC_CLKC_CLK_EN1 0x0004 -#define SIRFSOC_CLKC_REF_CFG 0x0014 -#define SIRFSOC_CLKC_CPU_CFG 0x0018 -#define SIRFSOC_CLKC_MEM_CFG 0x001c -#define SIRFSOC_CLKC_SYS_CFG 0x0020 -#define SIRFSOC_CLKC_IO_CFG 0x0024 -#define SIRFSOC_CLKC_DSP_CFG 0x0028 -#define SIRFSOC_CLKC_GFX_CFG 0x002c -#define SIRFSOC_CLKC_MM_CFG 0x0030 -#define SIRFSOC_LKC_LCD_CFG 0x0034 -#define SIRFSOC_CLKC_MMC_CFG 0x0038 -#define SIRFSOC_CLKC_PLL1_CFG0 0x0040 -#define SIRFSOC_CLKC_PLL2_CFG0 0x0044 -#define SIRFSOC_CLKC_PLL3_CFG0 0x0048 -#define SIRFSOC_CLKC_PLL1_CFG1 0x004c -#define SIRFSOC_CLKC_PLL2_CFG1 0x0050 -#define SIRFSOC_CLKC_PLL3_CFG1 0x0054 -#define SIRFSOC_CLKC_PLL1_CFG2 0x0058 -#define SIRFSOC_CLKC_PLL2_CFG2 0x005c -#define SIRFSOC_CLKC_PLL3_CFG2 0x0060 - -#define SIRFSOC_CLOCK_VA_BASE SIRFSOC_VA(0x005000) - -#define KHZ 1000 -#define MHZ (KHZ * KHZ) - -struct clk_ops { - unsigned long (*get_rate)(struct clk *clk); - long (*round_rate)(struct clk *clk, unsigned long rate); - int (*set_rate)(struct clk *clk, unsigned long rate); - int (*enable)(struct clk *clk); - int (*disable)(struct clk *clk); - struct clk *(*get_parent)(struct clk *clk); - int (*set_parent)(struct clk *clk, struct clk *parent); -}; - -struct clk { - struct clk *parent; /* parent clk */ - unsigned long rate; /* clock rate in Hz */ - signed char usage; /* clock enable count */ - signed char enable_bit; /* enable bit: 0 ~ 63 */ - unsigned short regofs; /* register offset */ - struct clk_ops *ops; /* clock operation */ -}; - -static DEFINE_SPINLOCK(clocks_lock); - -static inline unsigned long clkc_readl(unsigned reg) -{ - return readl(SIRFSOC_CLOCK_VA_BASE + reg); -} - -static inline void clkc_writel(u32 val, unsigned reg) -{ - writel(val, SIRFSOC_CLOCK_VA_BASE + reg); -} - -/* - * osc_rtc - real time oscillator - 32.768KHz - * osc_sys - high speed oscillator - 26MHz - */ - -static struct clk clk_rtc = { - .rate = 32768, -}; - -static struct clk clk_osc = { - .rate = 26 * MHZ, -}; - -/* - * std pll - */ -static unsigned long std_pll_get_rate(struct clk *clk) -{ - unsigned long fin = clk_get_rate(clk->parent); - u32 regcfg2 = clk->regofs + SIRFSOC_CLKC_PLL1_CFG2 - - SIRFSOC_CLKC_PLL1_CFG0; - - if (clkc_readl(regcfg2) & BIT(2)) { - /* pll bypass mode */ - clk->rate = fin; - } else { - /* fout = fin * nf / nr / od */ - u32 cfg0 = clkc_readl(clk->regofs); - u32 nf = (cfg0 & (BIT(13) - 1)) + 1; - u32 nr = ((cfg0 >> 13) & (BIT(6) - 1)) + 1; - u32 od = ((cfg0 >> 19) & (BIT(4) - 1)) + 1; - WARN_ON(fin % MHZ); - clk->rate = fin / MHZ * nf / nr / od * MHZ; - } - - return clk->rate; -} - -static int std_pll_set_rate(struct clk *clk, unsigned long rate) -{ - unsigned long fin, nf, nr, od, reg; - - /* - * fout = fin * nf / (nr * od); - * set od = 1, nr = fin/MHz, so fout = nf * MHz - */ - - nf = rate / MHZ; - if (unlikely((rate % MHZ) || nf > BIT(13) || nf < 1)) - return -EINVAL; - - fin = clk_get_rate(clk->parent); - BUG_ON(fin < MHZ); - - nr = fin / MHZ; - BUG_ON((fin % MHZ) || nr > BIT(6)); - - od = 1; - - reg = (nf - 1) | ((nr - 1) << 13) | ((od - 1) << 19); - clkc_writel(reg, clk->regofs); - - reg = clk->regofs + SIRFSOC_CLKC_PLL1_CFG1 - SIRFSOC_CLKC_PLL1_CFG0; - clkc_writel((nf >> 1) - 1, reg); - - reg = clk->regofs + SIRFSOC_CLKC_PLL1_CFG2 - SIRFSOC_CLKC_PLL1_CFG0; - while (!(clkc_readl(reg) & BIT(6))) - cpu_relax(); - - clk->rate = 0; /* set to zero will force recalculation */ - return 0; -} - -static struct clk_ops std_pll_ops = { - .get_rate = std_pll_get_rate, - .set_rate = std_pll_set_rate, -}; - -static struct clk clk_pll1 = { - .parent = &clk_osc, - .regofs = SIRFSOC_CLKC_PLL1_CFG0, - .ops = &std_pll_ops, -}; - -static struct clk clk_pll2 = { - .parent = &clk_osc, - .regofs = SIRFSOC_CLKC_PLL2_CFG0, - .ops = &std_pll_ops, -}; - -static struct clk clk_pll3 = { - .parent = &clk_osc, - .regofs = SIRFSOC_CLKC_PLL3_CFG0, - .ops = &std_pll_ops, -}; - -/* - * clock domains - cpu, mem, sys/io - */ - -static struct clk clk_mem; - -static struct clk *dmn_get_parent(struct clk *clk) -{ - struct clk *clks[] = { - &clk_osc, &clk_rtc, &clk_pll1, &clk_pll2, &clk_pll3 - }; - u32 cfg = clkc_readl(clk->regofs); - WARN_ON((cfg & (BIT(3) - 1)) > 4); - return clks[cfg & (BIT(3) - 1)]; -} - -static int dmn_set_parent(struct clk *clk, struct clk *parent) -{ - const struct clk *clks[] = { - &clk_osc, &clk_rtc, &clk_pll1, &clk_pll2, &clk_pll3 - }; - u32 cfg = clkc_readl(clk->regofs); - int i; - for (i = 0; i < ARRAY_SIZE(clks); i++) { - if (clks[i] == parent) { - cfg &= ~(BIT(3) - 1); - clkc_writel(cfg | i, clk->regofs); - /* BIT(3) - switching status: 1 - busy, 0 - done */ - while (clkc_readl(clk->regofs) & BIT(3)) - cpu_relax(); - return 0; - } - } - return -EINVAL; -} - -static unsigned long dmn_get_rate(struct clk *clk) -{ - unsigned long fin = clk_get_rate(clk->parent); - u32 cfg = clkc_readl(clk->regofs); - if (cfg & BIT(24)) { - /* fcd bypass mode */ - clk->rate = fin; - } else { - /* - * wait count: bit[19:16], hold count: bit[23:20] - */ - u32 wait = (cfg >> 16) & (BIT(4) - 1); - u32 hold = (cfg >> 20) & (BIT(4) - 1); - - clk->rate = fin / (wait + hold + 2); - } - - return clk->rate; -} - -static int dmn_set_rate(struct clk *clk, unsigned long rate) -{ - unsigned long fin; - unsigned ratio, wait, hold, reg; - unsigned bits = (clk == &clk_mem) ? 3 : 4; - - fin = clk_get_rate(clk->parent); - ratio = fin / rate; - - if (unlikely(ratio < 2 || ratio > BIT(bits + 1))) - return -EINVAL; - - WARN_ON(fin % rate); - - wait = (ratio >> 1) - 1; - hold = ratio - wait - 2; - - reg = clkc_readl(clk->regofs); - reg &= ~(((BIT(bits) - 1) << 16) | ((BIT(bits) - 1) << 20)); - reg |= (wait << 16) | (hold << 20) | BIT(25); - clkc_writel(reg, clk->regofs); - - /* waiting FCD been effective */ - while (clkc_readl(clk->regofs) & BIT(25)) - cpu_relax(); - - clk->rate = 0; /* set to zero will force recalculation */ - - return 0; -} - -/* - * cpu clock has no FCD register in Prima2, can only change pll - */ -static int cpu_set_rate(struct clk *clk, unsigned long rate) -{ - int ret1, ret2; - struct clk *cur_parent, *tmp_parent; - - cur_parent = dmn_get_parent(clk); - BUG_ON(cur_parent == NULL || cur_parent->usage > 1); - - /* switch to tmp pll before setting parent clock's rate */ - tmp_parent = cur_parent == &clk_pll1 ? &clk_pll2 : &clk_pll1; - ret1 = dmn_set_parent(clk, tmp_parent); - BUG_ON(ret1); - - ret2 = clk_set_rate(cur_parent, rate); - - ret1 = dmn_set_parent(clk, cur_parent); - - clk->rate = 0; /* set to zero will force recalculation */ - - return ret2 ? ret2 : ret1; -} - -static struct clk_ops cpu_ops = { - .get_parent = dmn_get_parent, - .set_parent = dmn_set_parent, - .set_rate = cpu_set_rate, -}; - -static struct clk clk_cpu = { - .parent = &clk_pll1, - .regofs = SIRFSOC_CLKC_CPU_CFG, - .ops = &cpu_ops, -}; - - -static struct clk_ops msi_ops = { - .set_rate = dmn_set_rate, - .get_rate = dmn_get_rate, - .set_parent = dmn_set_parent, - .get_parent = dmn_get_parent, -}; - -static struct clk clk_mem = { - .parent = &clk_pll2, - .regofs = SIRFSOC_CLKC_MEM_CFG, - .ops = &msi_ops, -}; - -static struct clk clk_sys = { - .parent = &clk_pll3, - .regofs = SIRFSOC_CLKC_SYS_CFG, - .ops = &msi_ops, -}; - -static struct clk clk_io = { - .parent = &clk_pll3, - .regofs = SIRFSOC_CLKC_IO_CFG, - .ops = &msi_ops, -}; - -/* - * on-chip clock sets - */ -static struct clk_lookup onchip_clks[] = { - { - .dev_id = "rtc", - .clk = &clk_rtc, - }, { - .dev_id = "osc", - .clk = &clk_osc, - }, { - .dev_id = "pll1", - .clk = &clk_pll1, - }, { - .dev_id = "pll2", - .clk = &clk_pll2, - }, { - .dev_id = "pll3", - .clk = &clk_pll3, - }, { - .dev_id = "cpu", - .clk = &clk_cpu, - }, { - .dev_id = "mem", - .clk = &clk_mem, - }, { - .dev_id = "sys", - .clk = &clk_sys, - }, { - .dev_id = "io", - .clk = &clk_io, - }, -}; - -int clk_enable(struct clk *clk) -{ - unsigned long flags; - - if (unlikely(IS_ERR_OR_NULL(clk))) - return -EINVAL; - - if (clk->parent) - clk_enable(clk->parent); - - spin_lock_irqsave(&clocks_lock, flags); - if (!clk->usage++ && clk->ops && clk->ops->enable) - clk->ops->enable(clk); - spin_unlock_irqrestore(&clocks_lock, flags); - return 0; -} -EXPORT_SYMBOL(clk_enable); - -void clk_disable(struct clk *clk) -{ - unsigned long flags; - - if (unlikely(IS_ERR_OR_NULL(clk))) - return; - - WARN_ON(!clk->usage); - - spin_lock_irqsave(&clocks_lock, flags); - if (--clk->usage == 0 && clk->ops && clk->ops->disable) - clk->ops->disable(clk); - spin_unlock_irqrestore(&clocks_lock, flags); - - if (clk->parent) - clk_disable(clk->parent); -} -EXPORT_SYMBOL(clk_disable); - -unsigned long clk_get_rate(struct clk *clk) -{ - if (unlikely(IS_ERR_OR_NULL(clk))) - return 0; - - if (clk->rate) - return clk->rate; - - if (clk->ops && clk->ops->get_rate) - return clk->ops->get_rate(clk); - - return clk_get_rate(clk->parent); -} -EXPORT_SYMBOL(clk_get_rate); - -long clk_round_rate(struct clk *clk, unsigned long rate) -{ - if (unlikely(IS_ERR_OR_NULL(clk))) - return 0; - - if (clk->ops && clk->ops->round_rate) - return clk->ops->round_rate(clk, rate); - - return 0; -} -EXPORT_SYMBOL(clk_round_rate); - -int clk_set_rate(struct clk *clk, unsigned long rate) -{ - if (unlikely(IS_ERR_OR_NULL(clk))) - return -EINVAL; - - if (!clk->ops || !clk->ops->set_rate) - return -EINVAL; - - return clk->ops->set_rate(clk, rate); -} -EXPORT_SYMBOL(clk_set_rate); - -int clk_set_parent(struct clk *clk, struct clk *parent) -{ - int ret; - unsigned long flags; - - if (unlikely(IS_ERR_OR_NULL(clk))) - return -EINVAL; - - if (!clk->ops || !clk->ops->set_parent) - return -EINVAL; - - spin_lock_irqsave(&clocks_lock, flags); - ret = clk->ops->set_parent(clk, parent); - if (!ret) { - parent->usage += clk->usage; - clk->parent->usage -= clk->usage; - BUG_ON(clk->parent->usage < 0); - clk->parent = parent; - } - spin_unlock_irqrestore(&clocks_lock, flags); - return ret; -} -EXPORT_SYMBOL(clk_set_parent); - -struct clk *clk_get_parent(struct clk *clk) -{ - unsigned long flags; - - if (unlikely(IS_ERR_OR_NULL(clk))) - return NULL; - - if (!clk->ops || !clk->ops->get_parent) - return clk->parent; - - spin_lock_irqsave(&clocks_lock, flags); - clk->parent = clk->ops->get_parent(clk); - spin_unlock_irqrestore(&clocks_lock, flags); - return clk->parent; -} -EXPORT_SYMBOL(clk_get_parent); - -static void __init sirfsoc_clk_init(void) -{ - clkdev_add_table(onchip_clks, ARRAY_SIZE(onchip_clks)); -} - -static struct of_device_id clkc_ids[] = { - { .compatible = "sirf,prima2-clkc" }, - {}, -}; - -void __init sirfsoc_of_clk_init(void) -{ - struct device_node *np; - struct resource res; - struct map_desc sirfsoc_clkc_iodesc = { - .virtual = SIRFSOC_CLOCK_VA_BASE, - .type = MT_DEVICE, - }; - - np = of_find_matching_node(NULL, clkc_ids); - if (!np) - panic("unable to find compatible clkc node in dtb\n"); - - if (of_address_to_resource(np, 0, &res)) - panic("unable to find clkc range in dtb"); - of_node_put(np); - - sirfsoc_clkc_iodesc.pfn = __phys_to_pfn(res.start); - sirfsoc_clkc_iodesc.length = 1 + res.end - res.start; - - iotable_init(&sirfsoc_clkc_iodesc, 1); - - sirfsoc_clk_init(); -} diff --git a/arch/arm/mach-prima2/prima2.c b/arch/arm/mach-prima2/common.c index 8f0429d4b79f..f25a54194639 100644 --- a/arch/arm/mach-prima2/prima2.c +++ b/arch/arm/mach-prima2/common.c @@ -30,21 +30,21 @@ void __init sirfsoc_init_late(void) sirfsoc_pm_init(); } -static const char *prima2cb_dt_match[] __initdata = { - "sirf,prima2-cb", +#ifdef CONFIG_ARCH_PRIMA2 +static const char *prima2_dt_match[] __initdata = { + "sirf,prima2", NULL }; -MACHINE_START(PRIMA2_EVB, "prima2cb") +DT_MACHINE_START(PRIMA2_DT, "Generic PRIMA2 (Flattened Device Tree)") /* Maintainer: Barry Song <baohua.song@csr.com> */ - .atag_offset = 0x100, - .init_early = sirfsoc_of_clk_init, .map_io = sirfsoc_map_lluart, .init_irq = sirfsoc_of_irq_init, .timer = &sirfsoc_timer, .dma_zone_size = SZ_256M, .init_machine = sirfsoc_mach_init, .init_late = sirfsoc_init_late, - .dt_compat = prima2cb_dt_match, + .dt_compat = prima2_dt_match, .restart = sirfsoc_restart, MACHINE_END +#endif diff --git a/arch/arm/mach-prima2/irq.c b/arch/arm/mach-prima2/irq.c index a7b9415d30f8..7dee9176e77a 100644 --- a/arch/arm/mach-prima2/irq.c +++ b/arch/arm/mach-prima2/irq.c @@ -63,7 +63,7 @@ void __init sirfsoc_of_irq_init(void) np = of_find_matching_node(NULL, intc_ids); if (!np) - panic("unable to find compatible intc node in dtb\n"); + return; sirfsoc_intc_base = of_iomap(np, 0); if (!sirfsoc_intc_base) diff --git a/arch/arm/mach-prima2/timer.c b/arch/arm/mach-prima2/timer.c index f224107de7bc..d95bf252f694 100644 --- a/arch/arm/mach-prima2/timer.c +++ b/arch/arm/mach-prima2/timer.c @@ -21,6 +21,8 @@ #include <asm/sched_clock.h> #include <asm/mach/time.h> +#include "common.h" + #define SIRFSOC_TIMER_COUNTER_LO 0x0000 #define SIRFSOC_TIMER_COUNTER_HI 0x0004 #define SIRFSOC_TIMER_MATCH_0 0x0008 @@ -188,9 +190,13 @@ static void __init sirfsoc_clockevent_init(void) static void __init sirfsoc_timer_init(void) { unsigned long rate; + struct clk *clk; + + /* initialize clocking early, we want to set the OS timer */ + sirfsoc_of_clk_init(); /* timer's input clock is io clock */ - struct clk *clk = clk_get_sys("io", NULL); + clk = clk_get_sys("io", NULL); BUG_ON(IS_ERR(clk)); diff --git a/arch/arm/mach-shark/core.c b/arch/arm/mach-shark/core.c index 2704bcd869cd..d35b94ef73b7 100644 --- a/arch/arm/mach-shark/core.c +++ b/arch/arm/mach-shark/core.c @@ -21,9 +21,6 @@ #include <asm/mach/arch.h> #include <asm/mach/time.h> -#define IO_BASE 0xe0000000 -#define IO_SIZE 0x08000000 -#define IO_START 0x40000000 #define ROMCARD_SIZE 0x08000000 #define ROMCARD_START 0x10000000 @@ -104,20 +101,6 @@ arch_initcall(shark_init); extern void shark_init_irq(void); -static struct map_desc shark_io_desc[] __initdata = { - { - .virtual = IO_BASE, - .pfn = __phys_to_pfn(IO_START), - .length = IO_SIZE, - .type = MT_DEVICE - } -}; - -static void __init shark_map_io(void) -{ - iotable_init(shark_io_desc, ARRAY_SIZE(shark_io_desc)); -} - #define IRQ_TIMER 0 #define HZ_TIME ((1193180 + HZ/2) / HZ) @@ -158,7 +141,6 @@ static void shark_init_early(void) MACHINE_START(SHARK, "Shark") /* Maintainer: Alexander Schulz */ .atag_offset = 0x3000, - .map_io = shark_map_io, .init_early = shark_init_early, .init_irq = shark_init_irq, .timer = &shark_timer, diff --git a/arch/arm/mach-shark/include/mach/debug-macro.S b/arch/arm/mach-shark/include/mach/debug-macro.S index 20eb2bf2a42b..d129119a3f69 100644 --- a/arch/arm/mach-shark/include/mach/debug-macro.S +++ b/arch/arm/mach-shark/include/mach/debug-macro.S @@ -12,9 +12,10 @@ */ .macro addruart, rp, rv, tmp - mov \rp, #0xe0000000 - orr \rp, \rp, #0x000003f8 - mov \rv, \rp + mov \rp, #0x3f8 + orr \rv, \rp, #0xfe000000 + orr \rv, \rv, #0x00e00000 + orr \rp, \rp, #0x40000000 .endm .macro senduart,rd,rx diff --git a/arch/arm/mach-shark/include/mach/entry-macro.S b/arch/arm/mach-shark/include/mach/entry-macro.S index 5901b09fc96a..c9e49f049532 100644 --- a/arch/arm/mach-shark/include/mach/entry-macro.S +++ b/arch/arm/mach-shark/include/mach/entry-macro.S @@ -8,7 +8,8 @@ * warranty of any kind, whether express or implied. */ .macro get_irqnr_preamble, base, tmp - mov \base, #0xe0000000 + mov \base, #0xfe000000 + orr \base, \base, #0x00e00000 .endm .macro get_irqnr_and_base, irqnr, irqstat, base, tmp diff --git a/arch/arm/mach-shark/include/mach/io.h b/arch/arm/mach-shark/include/mach/io.h deleted file mode 100644 index 1a45fc01ff1d..000000000000 --- a/arch/arm/mach-shark/include/mach/io.h +++ /dev/null @@ -1,18 +0,0 @@ -/* - * arch/arm/mach-shark/include/mach/io.h - * - * by Alexander Schulz - * - * derived from: - * arch/arm/mach-ebsa110/include/mach/io.h - * Copyright (C) 1997,1998 Russell King - */ - -#ifndef __ASM_ARM_ARCH_IO_H -#define __ASM_ARM_ARCH_IO_H - -#define IO_SPACE_LIMIT 0xffffffff - -#define __io(a) ((void __iomem *)(0xe0000000 + (a))) - -#endif diff --git a/arch/arm/mach-shark/pci.c b/arch/arm/mach-shark/pci.c index 9089407d5326..b8b4ab323a3e 100644 --- a/arch/arm/mach-shark/pci.c +++ b/arch/arm/mach-shark/pci.c @@ -8,12 +8,15 @@ #include <linux/kernel.h> #include <linux/pci.h> #include <linux/init.h> +#include <linux/io.h> #include <video/vga.h> #include <asm/irq.h> #include <asm/mach/pci.h> #include <asm/mach-types.h> +#define IO_START 0x40000000 + static int __init shark_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) { if (dev->bus->number == 0) @@ -44,6 +47,8 @@ static int __init shark_pci_init(void) pcibios_min_mem = 0x50000000; vga_base = 0xe8000000; + pci_ioremap_io(0, IO_START); + pci_common_init(&shark_pci); return 0; diff --git a/arch/arm/mach-tegra/include/mach/io.h b/arch/arm/mach-tegra/include/mach/io.h deleted file mode 100644 index fe700f9ce7dc..000000000000 --- a/arch/arm/mach-tegra/include/mach/io.h +++ /dev/null @@ -1,46 +0,0 @@ -/* - * arch/arm/mach-tegra/include/mach/io.h - * - * Copyright (C) 2010 Google, Inc. - * - * Author: - * Colin Cross <ccross@google.com> - * Erik Gilling <konkers@google.com> - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#ifndef __MACH_TEGRA_IO_H -#define __MACH_TEGRA_IO_H - -#define IO_SPACE_LIMIT 0xffff - -#ifndef __ASSEMBLER__ - -#ifdef CONFIG_TEGRA_PCI -extern void __iomem *tegra_pcie_io_base; - -static inline void __iomem *__io(unsigned long addr) -{ - return tegra_pcie_io_base + (addr & IO_SPACE_LIMIT); -} -#else -static inline void __iomem *__io(unsigned long addr) -{ - return (void __iomem *)addr; -} -#endif - -#define __io(a) __io(a) - -#endif - -#endif diff --git a/arch/arm/mach-tegra/include/mach/iomap.h b/arch/arm/mach-tegra/include/mach/iomap.h index 7e76da73121c..fee3a94c4549 100644 --- a/arch/arm/mach-tegra/include/mach/iomap.h +++ b/arch/arm/mach-tegra/include/mach/iomap.h @@ -303,6 +303,9 @@ #define IO_APB_VIRT IOMEM(0xFE300000) #define IO_APB_SIZE SZ_1M +#define TEGRA_PCIE_BASE 0x80000000 +#define TEGRA_PCIE_IO_BASE (TEGRA_PCIE_BASE + SZ_4M) + #define IO_TO_VIRT_BETWEEN(p, st, sz) ((p) >= (st) && (p) < ((st) + (sz))) #define IO_TO_VIRT_XLATE(p, pst, vst) (((p) - (pst) + (vst))) diff --git a/arch/arm/mach-tegra/pcie.c b/arch/arm/mach-tegra/pcie.c index d3ad5150d660..3463fb5b79c7 100644 --- a/arch/arm/mach-tegra/pcie.c +++ b/arch/arm/mach-tegra/pcie.c @@ -171,8 +171,6 @@ static void __iomem *reg_pmc_base = IO_ADDRESS(TEGRA_PMC_BASE); * 0x90000000 - 0x9fffffff - non-prefetchable memory * 0xa0000000 - 0xbfffffff - prefetchable memory */ -#define TEGRA_PCIE_BASE 0x80000000 - #define PCIE_REGS_SZ SZ_16K #define PCIE_CFG_OFF PCIE_REGS_SZ #define PCIE_CFG_SZ SZ_1M @@ -180,8 +178,6 @@ static void __iomem *reg_pmc_base = IO_ADDRESS(TEGRA_PMC_BASE); #define PCIE_EXT_CFG_SZ SZ_1M #define PCIE_IOMAP_SZ (PCIE_REGS_SZ + PCIE_CFG_SZ + PCIE_EXT_CFG_SZ) -#define MMIO_BASE (TEGRA_PCIE_BASE + SZ_4M) -#define MMIO_SIZE SZ_64K #define MEM_BASE_0 (TEGRA_PCIE_BASE + SZ_256M) #define MEM_SIZE_0 SZ_128M #define MEM_BASE_1 (MEM_BASE_0 + MEM_SIZE_0) @@ -204,10 +200,9 @@ struct tegra_pcie_port { bool link_up; - char io_space_name[16]; char mem_space_name[16]; char prefetch_space_name[20]; - struct resource res[3]; + struct resource res[2]; }; struct tegra_pcie_info { @@ -223,17 +218,7 @@ struct tegra_pcie_info { struct clk *pll_e; }; -static struct tegra_pcie_info tegra_pcie = { - .res_mmio = { - .name = "PCI IO", - .start = MMIO_BASE, - .end = MMIO_BASE + MMIO_SIZE - 1, - .flags = IORESOURCE_MEM, - }, -}; - -void __iomem *tegra_pcie_io_base; -EXPORT_SYMBOL(tegra_pcie_io_base); +static struct tegra_pcie_info tegra_pcie; static inline void afi_writel(u32 value, unsigned long offset) { @@ -391,24 +376,7 @@ static int tegra_pcie_setup(int nr, struct pci_sys_data *sys) pp = tegra_pcie.port + nr; pp->root_bus_nr = sys->busnr; - /* - * IORESOURCE_IO - */ - snprintf(pp->io_space_name, sizeof(pp->io_space_name), - "PCIe %d I/O", pp->index); - pp->io_space_name[sizeof(pp->io_space_name) - 1] = 0; - pp->res[0].name = pp->io_space_name; - if (pp->index == 0) { - pp->res[0].start = PCIBIOS_MIN_IO; - pp->res[0].end = pp->res[0].start + SZ_32K - 1; - } else { - pp->res[0].start = PCIBIOS_MIN_IO + SZ_32K; - pp->res[0].end = IO_SPACE_LIMIT; - } - pp->res[0].flags = IORESOURCE_IO; - if (request_resource(&ioport_resource, &pp->res[0])) - panic("Request PCIe IO resource failed\n"); - pci_add_resource_offset(&sys->resources, &pp->res[0], sys->io_offset); + pci_ioremap_io(nr * SZ_64K, TEGRA_PCIE_IO_BASE); /* * IORESOURCE_MEM @@ -416,18 +384,18 @@ static int tegra_pcie_setup(int nr, struct pci_sys_data *sys) snprintf(pp->mem_space_name, sizeof(pp->mem_space_name), "PCIe %d MEM", pp->index); pp->mem_space_name[sizeof(pp->mem_space_name) - 1] = 0; - pp->res[1].name = pp->mem_space_name; + pp->res[0].name = pp->mem_space_name; if (pp->index == 0) { - pp->res[1].start = MEM_BASE_0; - pp->res[1].end = pp->res[1].start + MEM_SIZE_0 - 1; + pp->res[0].start = MEM_BASE_0; + pp->res[0].end = pp->res[0].start + MEM_SIZE_0 - 1; } else { - pp->res[1].start = MEM_BASE_1; - pp->res[1].end = pp->res[1].start + MEM_SIZE_1 - 1; + pp->res[0].start = MEM_BASE_1; + pp->res[0].end = pp->res[0].start + MEM_SIZE_1 - 1; } - pp->res[1].flags = IORESOURCE_MEM; - if (request_resource(&iomem_resource, &pp->res[1])) + pp->res[0].flags = IORESOURCE_MEM; + if (request_resource(&iomem_resource, &pp->res[0])) panic("Request PCIe Memory resource failed\n"); - pci_add_resource_offset(&sys->resources, &pp->res[1], sys->mem_offset); + pci_add_resource_offset(&sys->resources, &pp->res[0], sys->mem_offset); /* * IORESOURCE_MEM | IORESOURCE_PREFETCH @@ -435,18 +403,18 @@ static int tegra_pcie_setup(int nr, struct pci_sys_data *sys) snprintf(pp->prefetch_space_name, sizeof(pp->prefetch_space_name), "PCIe %d PREFETCH MEM", pp->index); pp->prefetch_space_name[sizeof(pp->prefetch_space_name) - 1] = 0; - pp->res[2].name = pp->prefetch_space_name; + pp->res[1].name = pp->prefetch_space_name; if (pp->index == 0) { - pp->res[2].start = PREFETCH_MEM_BASE_0; - pp->res[2].end = pp->res[2].start + PREFETCH_MEM_SIZE_0 - 1; + pp->res[1].start = PREFETCH_MEM_BASE_0; + pp->res[1].end = pp->res[1].start + PREFETCH_MEM_SIZE_0 - 1; } else { - pp->res[2].start = PREFETCH_MEM_BASE_1; - pp->res[2].end = pp->res[2].start + PREFETCH_MEM_SIZE_1 - 1; + pp->res[1].start = PREFETCH_MEM_BASE_1; + pp->res[1].end = pp->res[1].start + PREFETCH_MEM_SIZE_1 - 1; } - pp->res[2].flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; - if (request_resource(&iomem_resource, &pp->res[2])) + pp->res[1].flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; + if (request_resource(&iomem_resource, &pp->res[1])) panic("Request PCIe Prefetch Memory resource failed\n"); - pci_add_resource_offset(&sys->resources, &pp->res[2], sys->mem_offset); + pci_add_resource_offset(&sys->resources, &pp->res[1], sys->mem_offset); return 1; } @@ -541,8 +509,8 @@ static void tegra_pcie_setup_translations(void) /* Bar 2: downstream IO bar */ fpci_bar = ((__u32)0xfdfc << 16); - size = MMIO_SIZE; - axi_address = MMIO_BASE; + size = SZ_128K; + axi_address = TEGRA_PCIE_IO_BASE; afi_writel(axi_address, AFI_AXI_BAR2_START); afi_writel(size >> 12, AFI_AXI_BAR2_SZ); afi_writel(fpci_bar, AFI_FPCI_BAR2); @@ -776,7 +744,6 @@ static void tegra_pcie_clocks_put(void) static int __init tegra_pcie_get_resources(void) { - struct resource *res_mmio = &tegra_pcie.res_mmio; int err; err = tegra_pcie_clocks_get(); @@ -798,34 +765,16 @@ static int __init tegra_pcie_get_resources(void) goto err_map_reg; } - err = request_resource(&iomem_resource, res_mmio); - if (err) { - pr_err("PCIE: Failed to request resources: %d\n", err); - goto err_req_io; - } - - tegra_pcie_io_base = ioremap_nocache(res_mmio->start, - resource_size(res_mmio)); - if (tegra_pcie_io_base == NULL) { - pr_err("PCIE: Failed to map IO\n"); - err = -ENOMEM; - goto err_map_io; - } - err = request_irq(INT_PCIE_INTR, tegra_pcie_isr, IRQF_SHARED, "PCIE", &tegra_pcie); if (err) { pr_err("PCIE: Failed to register IRQ: %d\n", err); - goto err_irq; + goto err_req_io; } set_irq_flags(INT_PCIE_INTR, IRQF_VALID); return 0; -err_irq: - iounmap(tegra_pcie_io_base); -err_map_io: - release_resource(&tegra_pcie.res_mmio); err_req_io: iounmap(tegra_pcie.regs); err_map_reg: diff --git a/arch/arm/mach-u300/Kconfig b/arch/arm/mach-u300/Kconfig index 54d8f34fdee5..f7e12ede008c 100644 --- a/arch/arm/mach-u300/Kconfig +++ b/arch/arm/mach-u300/Kconfig @@ -1,6 +1,6 @@ if ARCH_U300 -menu "ST-Ericsson AB U300/U330/U335/U365 Platform" +menu "ST-Ericsson AB U300/U335 Platform" comment "ST-Ericsson Mobile Platform Products" @@ -10,46 +10,7 @@ config MACH_U300 select PINCTRL_U300 select PINCTRL_COH901 -comment "ST-Ericsson U300/U330/U335/U365 Feature Selections" - -choice - prompt "U300/U330/U335/U365 system type" - default MACH_U300_BS2X - ---help--- - You need to select the target system, i.e. the - U300/U330/U335/U365 board that you want to compile your kernel - for. - -config MACH_U300_BS2X - bool "S26/S26/B25/B26 Test Products" - depends on MACH_U300 - help - Select this if you're developing on the - S26/S25 test products. (Also works on - B26/B25 big boards.) - -config MACH_U300_BS330 - bool "S330/B330 Test Products" - depends on MACH_U300 - help - Select this if you're developing on the - S330/B330 test products. - -config MACH_U300_BS335 - bool "S335/B335 Test Products" - depends on MACH_U300 - help - Select this if you're developing on the - S335/B335 test products. - -config MACH_U300_BS365 - bool "S365/B365 Test Products" - depends on MACH_U300 - help - Select this if you're developing on the - S365/B365 test products. - -endchoice +comment "ST-Ericsson U300/U335 Feature Selections" config U300_DEBUG bool "Debug support for U300" diff --git a/arch/arm/mach-u300/Makefile b/arch/arm/mach-u300/Makefile index 7e47d37aeb0e..5a86c58da396 100644 --- a/arch/arm/mach-u300/Makefile +++ b/arch/arm/mach-u300/Makefile @@ -7,7 +7,6 @@ obj-m := obj-n := obj- := -obj-$(CONFIG_ARCH_U300) += u300.o obj-$(CONFIG_SPI_PL022) += spi.o obj-$(CONFIG_MACH_U300_SPIDUMMY) += dummyspichip.o obj-$(CONFIG_I2C_STU300) += i2c.o diff --git a/arch/arm/mach-u300/core.c b/arch/arm/mach-u300/core.c index 03acf1883ec7..ef6f602b7e48 100644 --- a/arch/arm/mach-u300/core.c +++ b/arch/arm/mach-u300/core.c @@ -3,7 +3,7 @@ * arch/arm/mach-u300/core.c * * - * Copyright (C) 2007-2010 ST-Ericsson SA + * Copyright (C) 2007-2012 ST-Ericsson SA * License terms: GNU General Public License (GPL) version 2 * Core platform support, IRQ handling and device definitions. * Author: Linus Walleij <linus.walleij@stericsson.com> @@ -31,23 +31,26 @@ #include <linux/pinctrl/pinconf-generic.h> #include <linux/dma-mapping.h> #include <linux/platform_data/clk-u300.h> +#include <linux/platform_data/pinctrl-coh901.h> #include <asm/types.h> #include <asm/setup.h> #include <asm/memory.h> #include <asm/hardware/vic.h> #include <asm/mach/map.h> -#include <asm/mach/irq.h> +#include <asm/mach-types.h> +#include <asm/mach/arch.h> #include <mach/coh901318.h> #include <mach/hardware.h> #include <mach/syscon.h> -#include <mach/dma_channels.h> -#include <mach/gpio-u300.h> +#include <mach/irqs.h> +#include "timer.h" #include "spi.h" #include "i2c.h" #include "u300-gpio.h" +#include "dma_channels.h" /* * Static I/O mappings that are needed for booting the U300 platforms. The @@ -76,7 +79,7 @@ static struct map_desc u300_io_desc[] __initdata = { }, }; -void __init u300_map_io(void) +static void __init u300_map_io(void) { iotable_init(u300_io_desc, ARRAY_SIZE(u300_io_desc)); /* We enable a real big DMA buffer if need be. */ @@ -101,7 +104,6 @@ static AMBA_APB_DEVICE(uart0, "uart0", 0, U300_UART0_BASE, { IRQ_U300_UART0 }, &uart0_plat_data); /* The U335 have an additional UART1 on the APP CPU */ -#ifdef CONFIG_MACH_U300_BS335 static struct amba_pl011_data uart1_plat_data = { #ifdef CONFIG_COH901318 .dma_filter = coh901318_filter_id, @@ -113,7 +115,6 @@ static struct amba_pl011_data uart1_plat_data = { /* Fast device at 0x7000 offset */ static AMBA_APB_DEVICE(uart1, "uart1", 0, U300_UART1_BASE, { IRQ_U300_UART1 }, &uart1_plat_data); -#endif /* AHB device at 0x4000 offset */ static AMBA_APB_DEVICE(pl172, "pl172", 0, U300_EMIF_CFG_BASE, { }, NULL); @@ -152,9 +153,7 @@ static AMBA_APB_DEVICE(mmcsd, "mmci", 0, U300_MMCSD_BASE, */ static struct amba_device *amba_devs[] __initdata = { &uart0_device, -#ifdef CONFIG_MACH_U300_BS335 &uart1_device, -#endif &pl022_device, &pl172_device, &mmcsd_device, @@ -188,7 +187,6 @@ static struct resource gpio_resources[] = { .end = IRQ_U300_GPIO_PORT2, .flags = IORESOURCE_IRQ, }, -#if defined(CONFIG_MACH_U300_BS365) || defined(CONFIG_MACH_U300_BS335) { .name = "gpio3", .start = IRQ_U300_GPIO_PORT3, @@ -201,8 +199,6 @@ static struct resource gpio_resources[] = { .end = IRQ_U300_GPIO_PORT4, .flags = IORESOURCE_IRQ, }, -#endif -#ifdef CONFIG_MACH_U300_BS335 { .name = "gpio5", .start = IRQ_U300_GPIO_PORT5, @@ -215,7 +211,6 @@ static struct resource gpio_resources[] = { .end = IRQ_U300_GPIO_PORT6, .flags = IORESOURCE_IRQ, }, -#endif /* CONFIG_MACH_U300_BS335 */ }; static struct resource keypad_resources[] = { @@ -323,7 +318,6 @@ static struct resource dma_resource[] = { } }; -#ifdef CONFIG_MACH_U300_BS335 /* points out all dma slave channels. * Syntax is [A1, B1, A2, B2, .... ,-1,-1] * Select all channels from A to B, end of list is marked with -1,-1 @@ -336,14 +330,6 @@ static int dma_slave_channels[] = { static int dma_memcpy_channels[] = { U300_DMA_GENERAL_PURPOSE_0, U300_DMA_GENERAL_PURPOSE_8, -1, -1}; -#else /* CONFIG_MACH_U300_BS335 */ - -static int dma_slave_channels[] = {U300_DMA_MSL_TX_0, U300_DMA_SPI_RX, -1, -1}; -static int dma_memcpy_channels[] = { - U300_DMA_GENERAL_PURPOSE_0, U300_DMA_GENERAL_PURPOSE_10, -1, -1}; - -#endif - /** register dma for memory access * * active 1 means dma intends to access memory @@ -1395,7 +1381,6 @@ const struct coh_dma_channel chan_config[U300_DMA_CHANNELS] = { .param.ctrl_lli = flags_memcpy_lli, .param.ctrl_lli_last = flags_memcpy_lli_last, }, -#ifdef CONFIG_MACH_U300_BS335 { .number = U300_DMA_UART1_TX, .name = "UART1 TX", @@ -1406,28 +1391,6 @@ const struct coh_dma_channel chan_config[U300_DMA_CHANNELS] = { .name = "UART1 RX", .priority_high = 0, } -#else - { - .number = U300_DMA_GENERAL_PURPOSE_9, - .name = "GENERAL 09", - .priority_high = 0, - - .param.config = flags_memcpy_config, - .param.ctrl_lli_chained = flags_memcpy_lli_chained, - .param.ctrl_lli = flags_memcpy_lli, - .param.ctrl_lli_last = flags_memcpy_lli_last, - }, - { - .number = U300_DMA_GENERAL_PURPOSE_10, - .name = "GENERAL 10", - .priority_high = 0, - - .param.config = flags_memcpy_config, - .param.ctrl_lli_chained = flags_memcpy_lli_chained, - .param.ctrl_lli = flags_memcpy_lli, - .param.ctrl_lli_last = flags_memcpy_lli_last, - } -#endif }; @@ -1480,18 +1443,7 @@ static struct platform_device pinctrl_device = { * GPIO block, with different number of ports. */ static struct u300_gpio_platform u300_gpio_plat = { -#if defined(CONFIG_MACH_U300_BS2X) || defined(CONFIG_MACH_U300_BS330) - .variant = U300_GPIO_COH901335, - .ports = 3, -#endif -#ifdef CONFIG_MACH_U300_BS335 - .variant = U300_GPIO_COH901571_3_BS335, .ports = 7, -#endif -#ifdef CONFIG_MACH_U300_BS365 - .variant = U300_GPIO_COH901571_3_BS365, - .ports = 5, -#endif .gpio_base = 0, .gpio_irq_base = IRQ_U300_GPIO_BASE, .pinctrl_device = &pinctrl_device, @@ -1651,7 +1603,7 @@ static struct platform_device *platform_devs[] __initdata = { * together so some interrupts are connected to the first one and some * to the second one. */ -void __init u300_init_irq(void) +static void __init u300_init_irq(void) { u32 mask[2] = {0, 0}; struct clk *clk; @@ -1756,29 +1708,11 @@ static void __init u300_init_check_chip(void) printk(KERN_INFO "Initializing U300 system on %s baseband chip " \ "(chip ID 0x%04x)\n", chipname, val); -#ifdef CONFIG_MACH_U300_BS330 - if ((val & 0xFF00U) != 0xd800) { - printk(KERN_ERR "Platform configured for BS330 " \ - "with DB3200 but %s detected, expect problems!", - chipname); - } -#endif -#ifdef CONFIG_MACH_U300_BS335 if ((val & 0xFF00U) != 0xf000 && (val & 0xFF00U) != 0xf100) { printk(KERN_ERR "Platform configured for BS335 " \ " with DB3350 but %s detected, expect problems!", chipname); } -#endif -#ifdef CONFIG_MACH_U300_BS365 - if ((val & 0xFF00U) != 0xe800) { - printk(KERN_ERR "Platform configured for BS365 " \ - "with DB3210 but %s detected, expect problems!", - chipname); - } -#endif - - } /* @@ -1811,7 +1745,7 @@ static void __init u300_assign_physmem(void) } } -void __init u300_init_devices(void) +static void __init u300_init_machine(void) { int i; u16 val; @@ -1852,7 +1786,7 @@ void __init u300_init_devices(void) /* Forward declare this function from the watchdog */ void coh901327_watchdog_reset(void); -void u300_restart(char mode, const char *cmd) +static void u300_restart(char mode, const char *cmd) { switch (mode) { case 's': @@ -1868,3 +1802,15 @@ void u300_restart(char mode, const char *cmd) /* Wait for system do die/reset. */ while (1); } + +MACHINE_START(U300, "Ericsson AB U335 S335/B335 Prototype Board") + /* Maintainer: Linus Walleij <linus.walleij@stericsson.com> */ + .atag_offset = 0x100, + .map_io = u300_map_io, + .nr_irqs = NR_IRQS_U300, + .init_irq = u300_init_irq, + .handle_irq = vic_handle_irq, + .timer = &u300_timer, + .init_machine = u300_init_machine, + .restart = u300_restart, +MACHINE_END diff --git a/arch/arm/mach-u300/include/mach/dma_channels.h b/arch/arm/mach-u300/dma_channels.h index b239149ba0d0..4e8a88fbca49 100644 --- a/arch/arm/mach-u300/include/mach/dma_channels.h +++ b/arch/arm/mach-u300/dma_channels.h @@ -3,7 +3,7 @@ * arch/arm/mach-u300/include/mach/dma_channels.h * * - * Copyright (C) 2007-2009 ST-Ericsson + * Copyright (C) 2007-2012 ST-Ericsson * License terms: GNU General Public License (GPL) version 2 * Map file for the U300 dma driver. * Author: Per Friden <per.friden@stericsson.com> @@ -50,19 +50,10 @@ #define U300_DMA_GENERAL_PURPOSE_6 35 #define U300_DMA_GENERAL_PURPOSE_7 36 #define U300_DMA_GENERAL_PURPOSE_8 37 -#ifdef CONFIG_MACH_U300_BS335 #define U300_DMA_UART1_TX 38 #define U300_DMA_UART1_RX 39 -#else -#define U300_DMA_GENERAL_PURPOSE_9 38 -#define U300_DMA_GENERAL_PURPOSE_10 39 -#endif -#ifdef CONFIG_MACH_U300_BS335 #define U300_DMA_DEVICE_CHANNELS 32 -#else -#define U300_DMA_DEVICE_CHANNELS 30 -#endif #define U300_DMA_CHANNELS 40 diff --git a/arch/arm/mach-u300/i2c.c b/arch/arm/mach-u300/i2c.c index cb04bd6ab3e7..0d4620ed853c 100644 --- a/arch/arm/mach-u300/i2c.c +++ b/arch/arm/mach-u300/i2c.c @@ -1,7 +1,7 @@ /* * arch/arm/mach-u300/i2c.c * - * Copyright (C) 2009 ST-Ericsson AB + * Copyright (C) 2009-2012 ST-Ericsson AB * License terms: GNU General Public License (GPL) version 2 * * Register board i2c devices @@ -261,7 +261,6 @@ static struct i2c_board_info __initdata bus0_i2c_board_info[] = { }; static struct i2c_board_info __initdata bus1_i2c_board_info[] = { -#ifdef CONFIG_MACH_U300_BS335 { .type = "fwcam", .addr = 0x10, @@ -270,9 +269,6 @@ static struct i2c_board_info __initdata bus1_i2c_board_info[] = { .type = "fwcam", .addr = 0x5d, }, -#else - { }, -#endif }; void __init u300_i2c_register_board_devices(void) diff --git a/arch/arm/mach-u300/include/mach/clkdev.h b/arch/arm/mach-u300/include/mach/clkdev.h deleted file mode 100644 index 92e3cc872c66..000000000000 --- a/arch/arm/mach-u300/include/mach/clkdev.h +++ /dev/null @@ -1,7 +0,0 @@ -#ifndef __MACH_CLKDEV_H -#define __MACH_CLKDEV_H - -int __clk_get(struct clk *clk); -void __clk_put(struct clk *clk); - -#endif diff --git a/arch/arm/mach-u300/include/mach/gpio-u300.h b/arch/arm/mach-u300/include/mach/gpio-u300.h deleted file mode 100644 index e81400c1753a..000000000000 --- a/arch/arm/mach-u300/include/mach/gpio-u300.h +++ /dev/null @@ -1,37 +0,0 @@ -/* - * Copyright (C) 2007-2011 ST-Ericsson AB - * License terms: GNU General Public License (GPL) version 2 - * GPIO block resgister definitions and inline macros for - * U300 GPIO COH 901 335 or COH 901 571/3 - * Author: Linus Walleij <linus.walleij@stericsson.com> - */ - -#ifndef __MACH_U300_GPIO_U300_H -#define __MACH_U300_GPIO_U300_H - -/** - * enum u300_gpio_variant - the type of U300 GPIO employed - */ -enum u300_gpio_variant { - U300_GPIO_COH901335, - U300_GPIO_COH901571_3_BS335, - U300_GPIO_COH901571_3_BS365, -}; - -/** - * struct u300_gpio_platform - U300 GPIO platform data - * @variant: IP block variant - * @ports: number of GPIO block ports - * @gpio_base: first GPIO number for this block (use a free range) - * @gpio_irq_base: first GPIO IRQ number for this block (use a free range) - * @pinctrl_device: pin control device to spawn as child - */ -struct u300_gpio_platform { - enum u300_gpio_variant variant; - u8 ports; - int gpio_base; - int gpio_irq_base; - struct platform_device *pinctrl_device; -}; - -#endif /* __MACH_U300_GPIO_U300_H */ diff --git a/arch/arm/mach-u300/include/mach/irqs.h b/arch/arm/mach-u300/include/mach/irqs.h index ec09c1e07b1a..e27425a63fa1 100644 --- a/arch/arm/mach-u300/include/mach/irqs.h +++ b/arch/arm/mach-u300/include/mach/irqs.h @@ -3,7 +3,7 @@ * arch/arm/mach-u300/include/mach/irqs.h * * - * Copyright (C) 2006-2009 ST-Ericsson AB + * Copyright (C) 2006-2012 ST-Ericsson AB * License terms: GNU General Public License (GPL) version 2 * IRQ channel definitions for the U300 platforms. * Author: Linus Walleij <linus.walleij@stericsson.com> @@ -31,10 +31,6 @@ #define IRQ_U300_XGAM_GAMCON 14 #define IRQ_U300_XGAM_CDI 15 #define IRQ_U300_XGAM_CDICON 16 -#if defined(CONFIG_MACH_U300_BS2X) || defined(CONFIG_MACH_U300_BS330) -/* MMIACC not used on the DB3210 or DB3350 chips */ -#define IRQ_U300_XGAM_MMIACC 17 -#endif #define IRQ_U300_XGAM_PDI 18 #define IRQ_U300_XGAM_PDICON 19 #define IRQ_U300_XGAM_GAMEACC 20 @@ -55,8 +51,6 @@ #define IRQ_U300_GPIO_PORT1 34 #define IRQ_U300_GPIO_PORT2 35 -#if defined(CONFIG_MACH_U300_BS2X) || defined(CONFIG_MACH_U300_BS330) || \ - defined(CONFIG_MACH_U300_BS335) /* These are for DB3150, DB3200 and DB3350 */ #define IRQ_U300_WDOG 36 #define IRQ_U300_EVHIST 37 @@ -68,15 +62,8 @@ #define IRQ_U300_RTC 43 #define IRQ_U300_NFIF 44 #define IRQ_U300_NFIF2 45 -#endif - -/* DB3150 and DB3200 have only 45 IRQs */ -#if defined(CONFIG_MACH_U300_BS2X) || defined(CONFIG_MACH_U300_BS330) -#define U300_VIC_IRQS_END 46 -#endif /* The DB3350-specific interrupt lines */ -#ifdef CONFIG_MACH_U300_BS335 #define IRQ_U300_ISP_F0 46 #define IRQ_U300_ISP_F1 47 #define IRQ_U300_ISP_F2 48 @@ -89,25 +76,6 @@ #define IRQ_U300_GPIO_PORT5 55 #define IRQ_U300_GPIO_PORT6 56 #define U300_VIC_IRQS_END 57 -#endif - -/* The DB3210-specific interrupt lines */ -#ifdef CONFIG_MACH_U300_BS365 -#define IRQ_U300_GPIO_PORT3 36 -#define IRQ_U300_GPIO_PORT4 37 -#define IRQ_U300_WDOG 38 -#define IRQ_U300_EVHIST 39 -#define IRQ_U300_MSPRO 40 -#define IRQ_U300_MMCSD_MCIINTR0 41 -#define IRQ_U300_MMCSD_MCIINTR1 42 -#define IRQ_U300_I2C0 43 -#define IRQ_U300_I2C1 44 -#define IRQ_U300_RTC 45 -#define IRQ_U300_NFIF 46 -#define IRQ_U300_NFIF2 47 -#define IRQ_U300_SYSCON_PLL_LOCK 48 -#define U300_VIC_IRQS_END 49 -#endif /* Maximum 8*7 GPIO lines */ #ifdef CONFIG_PINCTRL_COH901 @@ -117,6 +85,6 @@ #define IRQ_U300_GPIO_END (U300_VIC_IRQS_END) #endif -#define NR_IRQS (IRQ_U300_GPIO_END - IRQ_U300_INTCON0_START) +#define NR_IRQS_U300 (IRQ_U300_GPIO_END - IRQ_U300_INTCON0_START) #endif diff --git a/arch/arm/mach-u300/include/mach/platform.h b/arch/arm/mach-u300/include/mach/platform.h deleted file mode 100644 index 096333f32fc3..000000000000 --- a/arch/arm/mach-u300/include/mach/platform.h +++ /dev/null @@ -1,20 +0,0 @@ -/* - * - * arch/arm/mach-u300/include/mach/platform.h - * - * - * Copyright (C) 2006-2009 ST-Ericsson AB - * License terms: GNU General Public License (GPL) version 2 - * Basic platform init and mapping functions. - * Author: Linus Walleij <linus.walleij@stericsson.com> - */ - -#ifndef __ASSEMBLY__ - -void u300_map_io(void); -void u300_init_irq(void); -void u300_init_devices(void); -void u300_restart(char, const char *); -extern struct sys_timer u300_timer; - -#endif diff --git a/arch/arm/mach-u300/include/mach/syscon.h b/arch/arm/mach-u300/include/mach/syscon.h index 6e84f07a7c6f..10bdd0be9774 100644 --- a/arch/arm/mach-u300/include/mach/syscon.h +++ b/arch/arm/mach-u300/include/mach/syscon.h @@ -3,7 +3,7 @@ * arch/arm/mach-u300/include/mach/syscon.h * * - * Copyright (C) 2008 ST-Ericsson AB + * Copyright (C) 2008-2012 ST-Ericsson AB * * Author: Rickard Andersson <rickard.andersson@stericsson.com> */ @@ -36,9 +36,7 @@ #define U300_SYSCON_CSR_PLL13_LOCK_IND (0x0001) /* Reset lines for SLOW devices 16bit (R/W) */ #define U300_SYSCON_RSR (0x0014) -#ifdef CONFIG_MACH_U300_BS335 #define U300_SYSCON_RSR_PPM_RESET_EN (0x0200) -#endif #define U300_SYSCON_RSR_ACC_TMR_RESET_EN (0x0100) #define U300_SYSCON_RSR_APP_TMR_RESET_EN (0x0080) #define U300_SYSCON_RSR_RTC_RESET_EN (0x0040) @@ -50,9 +48,7 @@ #define U300_SYSCON_RSR_SLOW_BRIDGE_RESET_EN (0x0001) /* Reset lines for FAST devices 16bit (R/W) */ #define U300_SYSCON_RFR (0x0018) -#ifdef CONFIG_MACH_U300_BS335 #define U300_SYSCON_RFR_UART1_RESET_ENABLE (0x0080) -#endif #define U300_SYSCON_RFR_SPI_RESET_ENABLE (0x0040) #define U300_SYSCON_RFR_MMC_RESET_ENABLE (0x0020) #define U300_SYSCON_RFR_PCM_I2S1_RESET_ENABLE (0x0010) @@ -62,10 +58,8 @@ #define U300_SYSCON_RFR_FAST_BRIDGE_RESET_ENABLE (0x0001) /* Reset lines for the rest of the peripherals 16bit (R/W) */ #define U300_SYSCON_RRR (0x001c) -#ifdef CONFIG_MACH_U300_BS335 #define U300_SYSCON_RRR_CDS_RESET_EN (0x4000) #define U300_SYSCON_RRR_ISP_RESET_EN (0x2000) -#endif #define U300_SYSCON_RRR_INTCON_RESET_EN (0x1000) #define U300_SYSCON_RRR_MSPRO_RESET_EN (0x0800) #define U300_SYSCON_RRR_XGAM_RESET_EN (0x0100) @@ -79,9 +73,7 @@ #define U300_SYSCON_RRR_AAIF_RESET_EN (0x0001) /* Clock enable for SLOW peripherals 16bit (R/W) */ #define U300_SYSCON_CESR (0x0020) -#ifdef CONFIG_MACH_U300_BS335 #define U300_SYSCON_CESR_PPM_CLK_EN (0x0200) -#endif #define U300_SYSCON_CESR_ACC_TMR_CLK_EN (0x0100) #define U300_SYSCON_CESR_APP_TMR_CLK_EN (0x0080) #define U300_SYSCON_CESR_KEYPAD_CLK_EN (0x0040) @@ -92,24 +84,20 @@ #define U300_SYSCON_CESR_SLOW_BRIDGE_CLK_EN (0x0001) /* Clock enable for FAST peripherals 16bit (R/W) */ #define U300_SYSCON_CEFR (0x0024) -#ifdef CONFIG_MACH_U300_BS335 #define U300_SYSCON_CEFR_UART1_CLK_EN (0x0200) -#endif #define U300_SYSCON_CEFR_I2S1_CORE_CLK_EN (0x0100) #define U300_SYSCON_CEFR_I2S0_CORE_CLK_EN (0x0080) #define U300_SYSCON_CEFR_SPI_CLK_EN (0x0040) #define U300_SYSCON_CEFR_MMC_CLK_EN (0x0020) -#define U300_SYSCON_CEFR_I2S1_CLK_EN (0x0010) -#define U300_SYSCON_CEFR_I2S0_CLK_EN (0x0008) -#define U300_SYSCON_CEFR_I2C1_CLK_EN (0x0004) -#define U300_SYSCON_CEFR_I2C0_CLK_EN (0x0002) +#define U300_SYSCON_CEFR_I2S1_CLK_EN (0x0010) +#define U300_SYSCON_CEFR_I2S0_CLK_EN (0x0008) +#define U300_SYSCON_CEFR_I2C1_CLK_EN (0x0004) +#define U300_SYSCON_CEFR_I2C0_CLK_EN (0x0002) #define U300_SYSCON_CEFR_FAST_BRIDGE_CLK_EN (0x0001) /* Clock enable for the rest of the peripherals 16bit (R/W) */ #define U300_SYSCON_CERR (0x0028) -#ifdef CONFIG_MACH_U300_BS335 #define U300_SYSCON_CERR_CDS_CLK_EN (0x2000) #define U300_SYSCON_CERR_ISP_CLK_EN (0x1000) -#endif #define U300_SYSCON_CERR_MSPRO_CLK_EN (0x0800) #define U300_SYSCON_CERR_AHB_SUBSYS_BRIDGE_CLK_EN (0x0400) #define U300_SYSCON_CERR_SEMI_CLK_EN (0x0200) @@ -124,9 +112,7 @@ #define U300_SYSCON_CERR_AAIF_CLK_EN (0x0001) /* Single block clock enable 16bit (-/W) */ #define U300_SYSCON_SBCER (0x002c) -#ifdef CONFIG_MACH_U300_BS335 #define U300_SYSCON_SBCER_PPM_CLK_EN (0x0009) -#endif #define U300_SYSCON_SBCER_ACC_TMR_CLK_EN (0x0008) #define U300_SYSCON_SBCER_APP_TMR_CLK_EN (0x0007) #define U300_SYSCON_SBCER_KEYPAD_CLK_EN (0x0006) @@ -135,9 +121,7 @@ #define U300_SYSCON_SBCER_BTR_CLK_EN (0x0002) #define U300_SYSCON_SBCER_UART_CLK_EN (0x0001) #define U300_SYSCON_SBCER_SLOW_BRIDGE_CLK_EN (0x0000) -#ifdef CONFIG_MACH_U300_BS335 #define U300_SYSCON_SBCER_UART1_CLK_EN (0x0019) -#endif #define U300_SYSCON_SBCER_I2S1_CORE_CLK_EN (0x0018) #define U300_SYSCON_SBCER_I2S0_CORE_CLK_EN (0x0017) #define U300_SYSCON_SBCER_SPI_CLK_EN (0x0016) @@ -147,10 +131,8 @@ #define U300_SYSCON_SBCER_I2C1_CLK_EN (0x0012) #define U300_SYSCON_SBCER_I2C0_CLK_EN (0x0011) #define U300_SYSCON_SBCER_FAST_BRIDGE_CLK_EN (0x0010) -#ifdef CONFIG_MACH_U300_BS335 #define U300_SYSCON_SBCER_CDS_CLK_EN (0x002D) #define U300_SYSCON_SBCER_ISP_CLK_EN (0x002C) -#endif #define U300_SYSCON_SBCER_MSPRO_CLK_EN (0x002B) #define U300_SYSCON_SBCER_AHB_SUBSYS_BRIDGE_CLK_EN (0x002A) #define U300_SYSCON_SBCER_SEMI_CLK_EN (0x0029) @@ -168,9 +150,7 @@ /* Same values as above for SBCER */ /* Clock force SLOW peripherals 16bit (R/W) */ #define U300_SYSCON_CFSR (0x003c) -#ifdef CONFIG_MACH_U300_BS335 #define U300_SYSCON_CFSR_PPM_CLK_FORCE_EN (0x0200) -#endif #define U300_SYSCON_CFSR_ACC_TMR_CLK_FORCE_EN (0x0100) #define U300_SYSCON_CFSR_APP_TMR_CLK_FORCE_EN (0x0080) #define U300_SYSCON_CFSR_KEYPAD_CLK_FORCE_EN (0x0020) @@ -184,10 +164,8 @@ /* Values not defined. Define if you want to use them. */ /* Clock force the rest of the peripherals 16bit (R/W) */ #define U300_SYSCON_CFRR (0x44) -#ifdef CONFIG_MACH_U300_BS335 #define U300_SYSCON_CFRR_CDS_CLK_FORCE_EN (0x2000) #define U300_SYSCON_CFRR_ISP_CLK_FORCE_EN (0x1000) -#endif #define U300_SYSCON_CFRR_MSPRO_CLK_FORCE_EN (0x0800) #define U300_SYSCON_CFRR_AHB_SUBSYS_BRIDGE_CLK_FORCE_EN (0x0400) #define U300_SYSCON_CFRR_SEMI_CLK_FORCE_EN (0x0200) diff --git a/arch/arm/mach-u300/include/mach/u300-regs.h b/arch/arm/mach-u300/include/mach/u300-regs.h index 65f87c523892..1e49d901f2c9 100644 --- a/arch/arm/mach-u300/include/mach/u300-regs.h +++ b/arch/arm/mach-u300/include/mach/u300-regs.h @@ -28,7 +28,6 @@ #define PLAT_NAND_CLE (1 << 16) #define PLAT_NAND_ALE (1 << 17) - /* AHB Peripherals */ #define U300_AHB_PER_PHYS_BASE 0xa0000000 #define U300_AHB_PER_VIRT_BASE 0xff010000 @@ -46,11 +45,7 @@ #define U300_BOOTROM_VIRT_BASE 0xffff0000 /* SEMI config base */ -#ifdef CONFIG_MACH_U300_BS335 #define U300_SEMI_CONFIG_BASE 0x2FFE0000 -#else -#define U300_SEMI_CONFIG_BASE 0x30000000 -#endif /* * AHB peripherals @@ -99,10 +94,8 @@ /* SPI controller */ #define U300_SPI_BASE (U300_FAST_PER_PHYS_BASE+0x6000) -#ifdef CONFIG_MACH_U300_BS335 /* Fast UART1 on U335 only */ #define U300_UART1_BASE (U300_SLOW_PER_PHYS_BASE+0x7000) -#endif /* * SLOW peripherals @@ -151,10 +144,8 @@ * REST peripherals */ -/* ISP (image signal processor) is only available in U335 */ -#ifdef CONFIG_MACH_U300_BS335 +/* ISP (image signal processor) */ #define U300_ISP_BASE (0xA0008000) -#endif /* DMA Controller base */ #define U300_DMAC_BASE (0xC0020000) @@ -166,17 +157,9 @@ #define U300_APEX_BASE (0xc0030000) /* Video Encoder Base */ -#ifdef CONFIG_MACH_U300_BS335 #define U300_VIDEOENC_BASE (0xc0080000) -#else -#define U300_VIDEOENC_BASE (0xc0040000) -#endif /* XGAM Base */ #define U300_XGAM_BASE (0xd0000000) -/* - * Virtual accessor macros for static devices - */ - #endif diff --git a/arch/arm/mach-u300/spi.c b/arch/arm/mach-u300/spi.c index a1affacfa59c..02e6659286d5 100644 --- a/arch/arm/mach-u300/spi.c +++ b/arch/arm/mach-u300/spi.c @@ -12,7 +12,7 @@ #include <linux/amba/pl022.h> #include <linux/err.h> #include <mach/coh901318.h> -#include <mach/dma_channels.h> +#include "dma_channels.h" /* * The following is for the actual devices on the SSP/SPI bus diff --git a/arch/arm/mach-u300/timer.c b/arch/arm/mach-u300/timer.c index 56ac06d38ec1..1da10e20e996 100644 --- a/arch/arm/mach-u300/timer.c +++ b/arch/arm/mach-u300/timer.c @@ -17,14 +17,17 @@ #include <linux/io.h> #include <linux/clk.h> #include <linux/err.h> +#include <linux/irq.h> #include <mach/hardware.h> +#include <mach/irqs.h> /* Generic stuff */ #include <asm/sched_clock.h> #include <asm/mach/map.h> #include <asm/mach/time.h> -#include <asm/mach/irq.h> + +#include "timer.h" /* * APP side special timer registers diff --git a/arch/arm/mach-u300/timer.h b/arch/arm/mach-u300/timer.h new file mode 100644 index 000000000000..b5e9791762e0 --- /dev/null +++ b/arch/arm/mach-u300/timer.h @@ -0,0 +1 @@ +extern struct sys_timer u300_timer; diff --git a/arch/arm/mach-u300/u300-gpio.h b/arch/arm/mach-u300/u300-gpio.h index 847dc25300c6..83f50772e169 100644 --- a/arch/arm/mach-u300/u300-gpio.h +++ b/arch/arm/mach-u300/u300-gpio.h @@ -1,50 +1,11 @@ /* - * Individual pin assignments for the B26/S26. Notice that the - * actual usage of these pins depends on the PAD MUX settings, that - * is why the same number can potentially appear several times. - * In the reference design each pin is only used for one purpose. - * These were determined by inspecting the B26/S26 schematic: - * 2/1911-ROA 128 1603 - */ -#ifdef CONFIG_MACH_U300_BS2X -#define U300_GPIO_PIN_UART_RX 0 -#define U300_GPIO_PIN_UART_TX 1 -#define U300_GPIO_PIN_GPIO02 2 /* Unrouted */ -#define U300_GPIO_PIN_GPIO03 3 /* Unrouted */ -#define U300_GPIO_PIN_CAM_SLEEP 4 -#define U300_GPIO_PIN_CAM_REG_EN 5 -#define U300_GPIO_PIN_GPIO06 6 /* Unrouted */ -#define U300_GPIO_PIN_GPIO07 7 /* Unrouted */ - -#define U300_GPIO_PIN_GPIO08 8 /* Service point SP2321 */ -#define U300_GPIO_PIN_GPIO09 9 /* Service point SP2322 */ -#define U300_GPIO_PIN_PHFSENSE 10 /* Headphone jack sensing */ -#define U300_GPIO_PIN_MMC_CLKRET 11 /* Clock return from MMC/SD card */ -#define U300_GPIO_PIN_MMC_CD 12 /* MMC Card insertion detection */ -#define U300_GPIO_PIN_FLIPSENSE 13 /* Mechanical flip sensing */ -#define U300_GPIO_PIN_GPIO14 14 /* DSP JTAG Port RTCK */ -#define U300_GPIO_PIN_GPIO15 15 /* Unrouted */ - -#define U300_GPIO_PIN_GPIO16 16 /* Unrouted */ -#define U300_GPIO_PIN_GPIO17 17 /* Unrouted */ -#define U300_GPIO_PIN_GPIO18 18 /* Unrouted */ -#define U300_GPIO_PIN_GPIO19 19 /* Unrouted */ -#define U300_GPIO_PIN_GPIO20 20 /* Unrouted */ -#define U300_GPIO_PIN_GPIO21 21 /* Unrouted */ -#define U300_GPIO_PIN_GPIO22 22 /* Unrouted */ -#define U300_GPIO_PIN_GPIO23 23 /* Unrouted */ -#endif - -/* - * Individual pin assignments for the B330/S330 and B365/S365. + * Individual pin assignments for the B335/S335. * Notice that the actual usage of these pins depends on the * PAD MUX settings, that is why the same number can potentially * appear several times. In the reference design each pin is only * used for one purpose. These were determined by inspecting the * S365 schematic. */ -#if defined(CONFIG_MACH_U300_BS330) || defined(CONFIG_MACH_U300_BS365) || \ - defined(CONFIG_MACH_U300_BS335) #define U300_GPIO_PIN_UART_RX 0 #define U300_GPIO_PIN_UART_TX 1 #define U300_GPIO_PIN_UART_CTS 2 @@ -90,8 +51,6 @@ #define U300_GPIO_PIN_GPIO38 38 /* Unrouted */ #define U300_GPIO_PIN_GPIO39 39 /* Unrouted */ -#ifdef CONFIG_MACH_U300_BS335 - #define U300_GPIO_PIN_GPIO40 40 /* Unrouted */ #define U300_GPIO_PIN_GPIO41 41 /* Unrouted */ #define U300_GPIO_PIN_GPIO42 42 /* Unrouted */ @@ -109,6 +68,3 @@ #define U300_GPIO_PIN_GPIO53 53 /* Unrouted */ #define U300_GPIO_PIN_GPIO54 54 /* Unrouted */ #define U300_GPIO_PIN_GPIO55 55 /* Unrouted */ -#endif - -#endif diff --git a/arch/arm/mach-u300/u300.c b/arch/arm/mach-u300/u300.c deleted file mode 100644 index f30c69d91d99..000000000000 --- a/arch/arm/mach-u300/u300.c +++ /dev/null @@ -1,57 +0,0 @@ -/* - * - * arch/arm/mach-u300/u300.c - * - * - * Copyright (C) 2006-2009 ST-Ericsson AB - * License terms: GNU General Public License (GPL) version 2 - * Platform machine definition. - * Author: Linus Walleij <linus.walleij@stericsson.com> - */ -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/mm.h> -#include <linux/sched.h> -#include <linux/interrupt.h> -#include <linux/ioport.h> -#include <linux/memblock.h> -#include <linux/platform_device.h> -#include <linux/io.h> -#include <mach/hardware.h> -#include <mach/platform.h> -#include <asm/hardware/vic.h> -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <asm/memory.h> - -static void __init u300_init_machine(void) -{ - u300_init_devices(); -} - -#ifdef CONFIG_MACH_U300_BS2X -#define MACH_U300_STRING "Ericsson AB U300 S25/S26/B25/B26 Prototype Board" -#endif - -#ifdef CONFIG_MACH_U300_BS330 -#define MACH_U300_STRING "Ericsson AB U330 S330/B330 Prototype Board" -#endif - -#ifdef CONFIG_MACH_U300_BS335 -#define MACH_U300_STRING "Ericsson AB U335 S335/B335 Prototype Board" -#endif - -#ifdef CONFIG_MACH_U300_BS365 -#define MACH_U300_STRING "Ericsson AB U365 S365/B365 Prototype Board" -#endif - -MACHINE_START(U300, MACH_U300_STRING) - /* Maintainer: Linus Walleij <linus.walleij@stericsson.com> */ - .atag_offset = 0x100, - .map_io = u300_map_io, - .init_irq = u300_init_irq, - .handle_irq = vic_handle_irq, - .timer = &u300_timer, - .init_machine = u300_init_machine, - .restart = u300_restart, -MACHINE_END diff --git a/arch/arm/mach-versatile/core.c b/arch/arm/mach-versatile/core.c index cd8ea3588f93..ca7902c6ed18 100644 --- a/arch/arm/mach-versatile/core.c +++ b/arch/arm/mach-versatile/core.c @@ -169,11 +169,6 @@ static struct map_desc versatile_io_desc[] __initdata = { .pfn = __phys_to_pfn(VERSATILE_PCI_CFG_BASE), .length = VERSATILE_PCI_CFG_BASE_SIZE, .type = MT_DEVICE - }, { - .virtual = (unsigned long)VERSATILE_PCI_VIRT_MEM_BASE0, - .pfn = __phys_to_pfn(VERSATILE_PCI_MEM_BASE0), - .length = IO_SPACE_LIMIT, - .type = MT_DEVICE }, #endif }; diff --git a/arch/arm/mach-versatile/include/mach/hardware.h b/arch/arm/mach-versatile/include/mach/hardware.h index 408e58da46c6..3e5d425e2a92 100644 --- a/arch/arm/mach-versatile/include/mach/hardware.h +++ b/arch/arm/mach-versatile/include/mach/hardware.h @@ -29,7 +29,6 @@ */ #define VERSATILE_PCI_VIRT_BASE (void __iomem *)0xe8000000ul #define VERSATILE_PCI_CFG_VIRT_BASE (void __iomem *)0xe9000000ul -#define VERSATILE_PCI_VIRT_MEM_BASE0 (void __iomem *)PCIO_BASE /* macro to get at MMIO space when running virtually */ #define IO_ADDRESS(x) (((x) & 0x0fffffff) + (((x) >> 4) & 0x0f000000) + 0xf0000000) diff --git a/arch/arm/mach-versatile/include/mach/io.h b/arch/arm/mach-versatile/include/mach/io.h deleted file mode 100644 index 0406513be7d8..000000000000 --- a/arch/arm/mach-versatile/include/mach/io.h +++ /dev/null @@ -1,27 +0,0 @@ -/* - * arch/arm/mach-versatile/include/mach/io.h - * - * Copyright (C) 2003 ARM Limited - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#ifndef __ASM_ARM_ARCH_IO_H -#define __ASM_ARM_ARCH_IO_H - -#define PCIO_BASE 0xeb000000ul - -#define __io(a) ((a) + PCIO_BASE) - -#endif diff --git a/arch/arm/mach-versatile/pci.c b/arch/arm/mach-versatile/pci.c index e95bf84cc837..2f84f4094f13 100644 --- a/arch/arm/mach-versatile/pci.c +++ b/arch/arm/mach-versatile/pci.c @@ -169,13 +169,6 @@ static struct pci_ops pci_versatile_ops = { .write = versatile_write_config, }; -static struct resource io_port = { - .name = "PCI", - .start = 0, - .end = IO_SPACE_LIMIT, - .flags = IORESOURCE_IO, -}; - static struct resource io_mem = { .name = "PCI I/O space", .start = VERSATILE_PCI_MEM_BASE0, @@ -207,12 +200,6 @@ static int __init pci_versatile_setup_resources(struct pci_sys_data *sys) "memory region (%d)\n", ret); goto out; } - ret = request_resource(&ioport_resource, &io_port); - if (ret) { - printk(KERN_ERR "PCI: unable to allocate I/O " - "port region (%d)\n", ret); - goto out; - } ret = request_resource(&iomem_resource, &non_mem); if (ret) { printk(KERN_ERR "PCI: unable to allocate non-prefetchable " @@ -227,11 +214,9 @@ static int __init pci_versatile_setup_resources(struct pci_sys_data *sys) } /* - * the IO resource for this bus * the mem resource for this bus * the prefetch mem resource for this bus */ - pci_add_resource_offset(&sys->resources, &io_port, sys->io_offset); pci_add_resource_offset(&sys->resources, &non_mem, sys->mem_offset); pci_add_resource_offset(&sys->resources, &pre_mem, sys->mem_offset); @@ -260,9 +245,11 @@ int __init pci_versatile_setup(int nr, struct pci_sys_data *sys) goto out; } + ret = pci_ioremap_io(0, VERSATILE_PCI_MEM_BASE0); + if (ret) + goto out; + if (nr == 0) { - sys->mem_offset = 0; - sys->io_offset = 0; ret = pci_versatile_setup_resources(sys); if (ret < 0) { printk("pci_versatile_setup: resources... oops?\n"); @@ -319,7 +306,6 @@ int __init pci_versatile_setup(int nr, struct pci_sys_data *sys) void __init pci_versatile_preinit(void) { - pcibios_min_io = 0x44000000; pcibios_min_mem = 0x50000000; __raw_writel(VERSATILE_PCI_MEM_BASE0 >> 28, PCI_IMAP0); diff --git a/arch/arm/mm/ioremap.c b/arch/arm/mm/ioremap.c index 566750fa57d4..9d869f93a3da 100644 --- a/arch/arm/mm/ioremap.c +++ b/arch/arm/mm/ioremap.c @@ -36,6 +36,7 @@ #include <asm/system_info.h> #include <asm/mach/map.h> +#include <asm/mach/pci.h> #include "mm.h" int ioremap_page(unsigned long virt, unsigned long phys, @@ -383,3 +384,16 @@ void __arm_iounmap(volatile void __iomem *io_addr) arch_iounmap(io_addr); } EXPORT_SYMBOL(__arm_iounmap); + +#ifdef CONFIG_PCI +int pci_ioremap_io(unsigned int offset, phys_addr_t phys_addr) +{ + BUG_ON(offset + SZ_64K > IO_SPACE_LIMIT); + + return ioremap_page_range(PCI_IO_VIRT_BASE + offset, + PCI_IO_VIRT_BASE + offset + SZ_64K, + phys_addr, + __pgprot(get_mem_type(MT_DEVICE)->prot_pte)); +} +EXPORT_SYMBOL_GPL(pci_ioremap_io); +#endif diff --git a/arch/arm/mm/mm.h b/arch/arm/mm/mm.h index 6776160618ef..a8ee92da3544 100644 --- a/arch/arm/mm/mm.h +++ b/arch/arm/mm/mm.h @@ -55,6 +55,9 @@ extern void __flush_dcache_page(struct address_space *mapping, struct page *page /* permanent static mappings from iotable_init() */ #define VM_ARM_STATIC_MAPPING 0x40000000 +/* empty mapping */ +#define VM_ARM_EMPTY_MAPPING 0x20000000 + /* mapping type (attributes) for permanent static mappings */ #define VM_ARM_MTYPE(mt) ((mt) << 20) #define VM_ARM_MTYPE_MASK (0x1f << 20) diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c index 4c2d0451e84a..a7a9e41fa2c2 100644 --- a/arch/arm/mm/mmu.c +++ b/arch/arm/mm/mmu.c @@ -31,6 +31,7 @@ #include <asm/mach/arch.h> #include <asm/mach/map.h> +#include <asm/mach/pci.h> #include "mm.h" @@ -216,7 +217,7 @@ static struct mem_type mem_types[] = { .prot_l1 = PMD_TYPE_TABLE, .prot_sect = PROT_SECT_DEVICE | PMD_SECT_WB, .domain = DOMAIN_IO, - }, + }, [MT_DEVICE_WC] = { /* ioremap_wc */ .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_WC, .prot_l1 = PMD_TYPE_TABLE, @@ -777,14 +778,27 @@ void __init iotable_init(struct map_desc *io_desc, int nr) create_mapping(md); vm->addr = (void *)(md->virtual & PAGE_MASK); vm->size = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK)); - vm->phys_addr = __pfn_to_phys(md->pfn); - vm->flags = VM_IOREMAP | VM_ARM_STATIC_MAPPING; + vm->phys_addr = __pfn_to_phys(md->pfn); + vm->flags = VM_IOREMAP | VM_ARM_STATIC_MAPPING; vm->flags |= VM_ARM_MTYPE(md->type); vm->caller = iotable_init; vm_area_add_early(vm++); } } +void __init vm_reserve_area_early(unsigned long addr, unsigned long size, + void *caller) +{ + struct vm_struct *vm; + + vm = early_alloc_aligned(sizeof(*vm), __alignof__(*vm)); + vm->addr = (void *)addr; + vm->size = size; + vm->flags = VM_IOREMAP | VM_ARM_EMPTY_MAPPING; + vm->caller = caller; + vm_area_add_early(vm); +} + #ifndef CONFIG_ARM_LPAE /* @@ -802,14 +816,7 @@ void __init iotable_init(struct map_desc *io_desc, int nr) static void __init pmd_empty_section_gap(unsigned long addr) { - struct vm_struct *vm; - - vm = early_alloc_aligned(sizeof(*vm), __alignof__(*vm)); - vm->addr = (void *)addr; - vm->size = SECTION_SIZE; - vm->flags = VM_IOREMAP | VM_ARM_STATIC_MAPPING; - vm->caller = pmd_empty_section_gap; - vm_area_add_early(vm); + vm_reserve_area_early(addr, SECTION_SIZE, pmd_empty_section_gap); } static void __init fill_pmd_gaps(void) @@ -820,7 +827,7 @@ static void __init fill_pmd_gaps(void) /* we're still single threaded hence no lock needed here */ for (vm = vmlist; vm; vm = vm->next) { - if (!(vm->flags & VM_ARM_STATIC_MAPPING)) + if (!(vm->flags & (VM_ARM_STATIC_MAPPING | VM_ARM_EMPTY_MAPPING))) continue; addr = (unsigned long)vm->addr; if (addr < next) @@ -858,6 +865,28 @@ static void __init fill_pmd_gaps(void) #define fill_pmd_gaps() do { } while (0) #endif +#if defined(CONFIG_PCI) && !defined(CONFIG_NEED_MACH_IO_H) +static void __init pci_reserve_io(void) +{ + struct vm_struct *vm; + unsigned long addr; + + /* we're still single threaded hence no lock needed here */ + for (vm = vmlist; vm; vm = vm->next) { + if (!(vm->flags & VM_ARM_STATIC_MAPPING)) + continue; + addr = (unsigned long)vm->addr; + addr &= ~(SZ_2M - 1); + if (addr == PCI_IO_VIRT_BASE) + return; + + } + vm_reserve_area_early(PCI_IO_VIRT_BASE, SZ_2M, pci_reserve_io); +} +#else +#define pci_reserve_io() do { } while (0) +#endif + static void * __initdata vmalloc_min = (void *)(VMALLOC_END - (240 << 20) - VMALLOC_OFFSET); @@ -1141,6 +1170,9 @@ static void __init devicemaps_init(struct machine_desc *mdesc) mdesc->map_io(); fill_pmd_gaps(); + /* Reserve fixed i/o space in VMALLOC region */ + pci_reserve_io(); + /* * Finally flush the caches and tlb to ensure that we're in a * consistent state wrt the writebuffer. This also ensures that diff --git a/arch/arm/plat-iop/pci.c b/arch/arm/plat-iop/pci.c index 8daae9b230ea..362474b5c40d 100644 --- a/arch/arm/plat-iop/pci.c +++ b/arch/arm/plat-iop/pci.c @@ -192,30 +192,24 @@ int iop3xx_pci_setup(int nr, struct pci_sys_data *sys) if (nr != 0) return 0; - res = kzalloc(2 * sizeof(struct resource), GFP_KERNEL); + res = kzalloc(sizeof(struct resource), GFP_KERNEL); if (!res) panic("PCI: unable to alloc resources"); - res[0].start = IOP3XX_PCI_LOWER_IO_PA; - res[0].end = IOP3XX_PCI_LOWER_IO_PA + IOP3XX_PCI_IO_WINDOW_SIZE - 1; - res[0].name = "IOP3XX PCI I/O Space"; - res[0].flags = IORESOURCE_IO; - request_resource(&ioport_resource, &res[0]); - - res[1].start = IOP3XX_PCI_LOWER_MEM_PA; - res[1].end = IOP3XX_PCI_LOWER_MEM_PA + IOP3XX_PCI_MEM_WINDOW_SIZE - 1; - res[1].name = "IOP3XX PCI Memory Space"; - res[1].flags = IORESOURCE_MEM; - request_resource(&iomem_resource, &res[1]); + res->start = IOP3XX_PCI_LOWER_MEM_PA; + res->end = IOP3XX_PCI_LOWER_MEM_PA + IOP3XX_PCI_MEM_WINDOW_SIZE - 1; + res->name = "IOP3XX PCI Memory Space"; + res->flags = IORESOURCE_MEM; + request_resource(&iomem_resource, res); /* * Use whatever translation is already setup. */ sys->mem_offset = IOP3XX_PCI_LOWER_MEM_PA - *IOP3XX_OMWTVR0; - sys->io_offset = IOP3XX_PCI_LOWER_IO_PA - *IOP3XX_OIOWTVR; - pci_add_resource_offset(&sys->resources, &res[0], sys->io_offset); - pci_add_resource_offset(&sys->resources, &res[1], sys->mem_offset); + pci_add_resource_offset(&sys->resources, res, sys->mem_offset); + + pci_ioremap_io(0, IOP3XX_PCI_LOWER_IO_PA); return 1; } @@ -367,7 +361,6 @@ void __init iop3xx_pci_preinit_cond(void) void __init iop3xx_pci_preinit(void) { - pcibios_min_io = 0; pcibios_min_mem = 0; iop3xx_atu_disable(); diff --git a/arch/arm/plat-iop/setup.c b/arch/arm/plat-iop/setup.c index bade586fed0f..5b217f460f18 100644 --- a/arch/arm/plat-iop/setup.c +++ b/arch/arm/plat-iop/setup.c @@ -25,11 +25,6 @@ static struct map_desc iop3xx_std_desc[] __initdata = { .pfn = __phys_to_pfn(IOP3XX_PERIPHERAL_PHYS_BASE), .length = IOP3XX_PERIPHERAL_SIZE, .type = MT_UNCACHED, - }, { /* PCI IO space */ - .virtual = IOP3XX_PCI_LOWER_IO_VA, - .pfn = __phys_to_pfn(IOP3XX_PCI_LOWER_IO_PA), - .length = IOP3XX_PCI_IO_WINDOW_SIZE, - .type = MT_DEVICE, }, }; |