diff options
Diffstat (limited to 'arch/arm/mach-lpc32xx')
-rw-r--r-- | arch/arm/mach-lpc32xx/Kconfig | 32 | ||||
-rw-r--r-- | arch/arm/mach-lpc32xx/Makefile.boot | 1 | ||||
-rw-r--r-- | arch/arm/mach-lpc32xx/clock.c | 123 | ||||
-rw-r--r-- | arch/arm/mach-lpc32xx/common.c | 10 | ||||
-rw-r--r-- | arch/arm/mach-lpc32xx/include/mach/gpio.h | 2 | ||||
-rw-r--r-- | arch/arm/mach-lpc32xx/include/mach/platform.h | 14 | ||||
-rw-r--r-- | arch/arm/mach-lpc32xx/phy3250.c | 163 | ||||
-rw-r--r-- | arch/arm/mach-lpc32xx/serial.c | 90 |
8 files changed, 195 insertions, 240 deletions
diff --git a/arch/arm/mach-lpc32xx/Kconfig b/arch/arm/mach-lpc32xx/Kconfig deleted file mode 100644 index e0b3eee83834..000000000000 --- a/arch/arm/mach-lpc32xx/Kconfig +++ /dev/null @@ -1,32 +0,0 @@ -if ARCH_LPC32XX - -menu "Individual UART enable selections" - -config ARCH_LPC32XX_UART3_SELECT - bool "Add support for standard UART3" - help - Adds support for standard UART 3 when the 8250 serial support - is enabled. - -config ARCH_LPC32XX_UART4_SELECT - bool "Add support for standard UART4" - help - Adds support for standard UART 4 when the 8250 serial support - is enabled. - -config ARCH_LPC32XX_UART5_SELECT - bool "Add support for standard UART5" - default y - help - Adds support for standard UART 5 when the 8250 serial support - is enabled. - -config ARCH_LPC32XX_UART6_SELECT - bool "Add support for standard UART6" - help - Adds support for standard UART 6 when the 8250 serial support - is enabled. - -endmenu - -endif diff --git a/arch/arm/mach-lpc32xx/Makefile.boot b/arch/arm/mach-lpc32xx/Makefile.boot index 2cfe0ee635c5..697323b5f92d 100644 --- a/arch/arm/mach-lpc32xx/Makefile.boot +++ b/arch/arm/mach-lpc32xx/Makefile.boot @@ -2,3 +2,4 @@ params_phys-y := 0x80000100 initrd_phys-y := 0x82000000 +dtb-$(CONFIG_ARCH_LPC32XX) += ea3250.dtb phy3250.dtb diff --git a/arch/arm/mach-lpc32xx/clock.c b/arch/arm/mach-lpc32xx/clock.c index f6a3ffec1f4b..f48c2e961b84 100644 --- a/arch/arm/mach-lpc32xx/clock.c +++ b/arch/arm/mach-lpc32xx/clock.c @@ -607,6 +607,19 @@ static struct clk clk_dma = { .get_rate = local_return_parent_rate, }; +static struct clk clk_pwm = { + .parent = &clk_pclk, + .enable = local_onoff_enable, + .enable_reg = LPC32XX_CLKPWR_PWM_CLK_CTRL, + .enable_mask = LPC32XX_CLKPWR_PWMCLK_PWM1CLK_EN | + LPC32XX_CLKPWR_PWMCLK_PWM1SEL_PCLK | + LPC32XX_CLKPWR_PWMCLK_PWM1_DIV(1) | + LPC32XX_CLKPWR_PWMCLK_PWM2CLK_EN | + LPC32XX_CLKPWR_PWMCLK_PWM2SEL_PCLK | + LPC32XX_CLKPWR_PWMCLK_PWM2_DIV(1), + .get_rate = local_return_parent_rate, +}; + static struct clk clk_uart3 = { .parent = &clk_pclk, .enable = local_onoff_enable, @@ -691,10 +704,21 @@ static struct clk clk_nand = { .parent = &clk_hclk, .enable = local_onoff_enable, .enable_reg = LPC32XX_CLKPWR_NAND_CLK_CTRL, - .enable_mask = LPC32XX_CLKPWR_NANDCLK_SLCCLK_EN, + .enable_mask = LPC32XX_CLKPWR_NANDCLK_SLCCLK_EN | + LPC32XX_CLKPWR_NANDCLK_SEL_SLC, .get_rate = local_return_parent_rate, }; +static struct clk clk_nand_mlc = { + .parent = &clk_hclk, + .enable = local_onoff_enable, + .enable_reg = LPC32XX_CLKPWR_NAND_CLK_CTRL, + .enable_mask = LPC32XX_CLKPWR_NANDCLK_MLCCLK_EN | + LPC32XX_CLKPWR_NANDCLK_DMA_INT | + LPC32XX_CLKPWR_NANDCLK_INTSEL_MLC, + .get_rate = local_return_parent_rate, +}; + static struct clk clk_i2s0 = { .parent = &clk_hclk, .enable = local_onoff_enable, @@ -707,7 +731,8 @@ static struct clk clk_i2s1 = { .parent = &clk_hclk, .enable = local_onoff_enable, .enable_reg = LPC32XX_CLKPWR_I2S_CLK_CTRL, - .enable_mask = LPC32XX_CLKPWR_I2SCTRL_I2SCLK1_EN, + .enable_mask = LPC32XX_CLKPWR_I2SCTRL_I2SCLK1_EN | + LPC32XX_CLKPWR_I2SCTRL_I2S1_USE_DMA, .get_rate = local_return_parent_rate, }; @@ -727,14 +752,77 @@ static struct clk clk_rtc = { .get_rate = local_return_parent_rate, }; +static int local_usb_enable(struct clk *clk, int enable) +{ + u32 tmp; + + if (enable) { + /* Set up I2C pull levels */ + tmp = __raw_readl(LPC32XX_CLKPWR_I2C_CLK_CTRL); + tmp |= LPC32XX_CLKPWR_I2CCLK_USBI2CHI_DRIVE; + __raw_writel(tmp, LPC32XX_CLKPWR_I2C_CLK_CTRL); + } + + return local_onoff_enable(clk, enable); +} + static struct clk clk_usbd = { .parent = &clk_usbpll, - .enable = local_onoff_enable, + .enable = local_usb_enable, .enable_reg = LPC32XX_CLKPWR_USB_CTRL, .enable_mask = LPC32XX_CLKPWR_USBCTRL_HCLK_EN, .get_rate = local_return_parent_rate, }; +#define OTG_ALWAYS_MASK (LPC32XX_USB_OTG_OTG_CLOCK_ON | \ + LPC32XX_USB_OTG_I2C_CLOCK_ON) + +static int local_usb_otg_enable(struct clk *clk, int enable) +{ + int to = 1000; + + if (enable) { + __raw_writel(clk->enable_mask, clk->enable_reg); + + while (((__raw_readl(LPC32XX_USB_OTG_CLK_STAT) & + clk->enable_mask) != clk->enable_mask) && (to > 0)) + to--; + } else { + __raw_writel(OTG_ALWAYS_MASK, clk->enable_reg); + + while (((__raw_readl(LPC32XX_USB_OTG_CLK_STAT) & + OTG_ALWAYS_MASK) != OTG_ALWAYS_MASK) && (to > 0)) + to--; + } + + if (to) + return 0; + else + return -1; +} + +static struct clk clk_usb_otg_dev = { + .parent = &clk_usbpll, + .enable = local_usb_otg_enable, + .enable_reg = LPC32XX_USB_OTG_CLK_CTRL, + .enable_mask = LPC32XX_USB_OTG_AHB_M_CLOCK_ON | + LPC32XX_USB_OTG_OTG_CLOCK_ON | + LPC32XX_USB_OTG_DEV_CLOCK_ON | + LPC32XX_USB_OTG_I2C_CLOCK_ON, + .get_rate = local_return_parent_rate, +}; + +static struct clk clk_usb_otg_host = { + .parent = &clk_usbpll, + .enable = local_usb_otg_enable, + .enable_reg = LPC32XX_USB_OTG_CLK_CTRL, + .enable_mask = LPC32XX_USB_OTG_AHB_M_CLOCK_ON | + LPC32XX_USB_OTG_OTG_CLOCK_ON | + LPC32XX_USB_OTG_HOST_CLOCK_ON | + LPC32XX_USB_OTG_I2C_CLOCK_ON, + .get_rate = local_return_parent_rate, +}; + static int tsc_onoff_enable(struct clk *clk, int enable) { u32 tmp; @@ -800,11 +888,17 @@ static int mmc_onoff_enable(struct clk *clk, int enable) u32 tmp; tmp = __raw_readl(LPC32XX_CLKPWR_MS_CTRL) & - ~LPC32XX_CLKPWR_MSCARD_SDCARD_EN; + ~(LPC32XX_CLKPWR_MSCARD_SDCARD_EN | + LPC32XX_CLKPWR_MSCARD_MSDIO_PU_EN | + LPC32XX_CLKPWR_MSCARD_MSDIO_PIN_DIS | + LPC32XX_CLKPWR_MSCARD_MSDIO0_DIS | + LPC32XX_CLKPWR_MSCARD_MSDIO1_DIS | + LPC32XX_CLKPWR_MSCARD_MSDIO23_DIS); /* If rate is 0, disable clock */ if (enable != 0) - tmp |= LPC32XX_CLKPWR_MSCARD_SDCARD_EN; + tmp |= LPC32XX_CLKPWR_MSCARD_SDCARD_EN | + LPC32XX_CLKPWR_MSCARD_MSDIO_PU_EN; __raw_writel(tmp, LPC32XX_CLKPWR_MS_CTRL); @@ -853,7 +947,7 @@ static unsigned long mmc_round_rate(struct clk *clk, unsigned long rate) static int mmc_set_rate(struct clk *clk, unsigned long rate) { - u32 oldclk, tmp; + u32 tmp; unsigned long prate, div, crate = mmc_round_rate(clk, rate); prate = clk->parent->get_rate(clk->parent); @@ -861,16 +955,12 @@ static int mmc_set_rate(struct clk *clk, unsigned long rate) div = prate / crate; /* The MMC clock must be on when accessing an MMC register */ - oldclk = __raw_readl(LPC32XX_CLKPWR_MS_CTRL); - __raw_writel(oldclk | LPC32XX_CLKPWR_MSCARD_SDCARD_EN, - LPC32XX_CLKPWR_MS_CTRL); tmp = __raw_readl(LPC32XX_CLKPWR_MS_CTRL) & ~LPC32XX_CLKPWR_MSCARD_SDCARD_DIV(0xf); - tmp |= LPC32XX_CLKPWR_MSCARD_SDCARD_DIV(div); + tmp |= LPC32XX_CLKPWR_MSCARD_SDCARD_DIV(div) | + LPC32XX_CLKPWR_MSCARD_SDCARD_EN; __raw_writel(tmp, LPC32XX_CLKPWR_MS_CTRL); - __raw_writel(oldclk, LPC32XX_CLKPWR_MS_CTRL); - return 0; } @@ -1111,6 +1201,7 @@ static struct clk_lookup lookups[] = { CLKDEV_INIT(NULL, "vfp9_ck", &clk_vfp9), CLKDEV_INIT("pl08xdmac", NULL, &clk_dma), CLKDEV_INIT("4003c000.watchdog", NULL, &clk_wdt), + CLKDEV_INIT("4005c000.pwm", NULL, &clk_pwm), CLKDEV_INIT(NULL, "uart3_ck", &clk_uart3), CLKDEV_INIT(NULL, "uart4_ck", &clk_uart4), CLKDEV_INIT(NULL, "uart5_ck", &clk_uart5), @@ -1120,8 +1211,9 @@ static struct clk_lookup lookups[] = { CLKDEV_INIT("31020300.i2c", NULL, &clk_i2c2), CLKDEV_INIT("dev:ssp0", NULL, &clk_ssp0), CLKDEV_INIT("dev:ssp1", NULL, &clk_ssp1), - CLKDEV_INIT("lpc32xx_keys.0", NULL, &clk_kscan), - CLKDEV_INIT("lpc32xx-nand.0", "nand_ck", &clk_nand), + CLKDEV_INIT("40050000.key", NULL, &clk_kscan), + CLKDEV_INIT("20020000.flash", NULL, &clk_nand), + CLKDEV_INIT("200a8000.flash", NULL, &clk_nand_mlc), CLKDEV_INIT("40048000.adc", NULL, &clk_adc), CLKDEV_INIT(NULL, "i2s0_ck", &clk_i2s0), CLKDEV_INIT(NULL, "i2s1_ck", &clk_i2s1), @@ -1130,6 +1222,9 @@ static struct clk_lookup lookups[] = { CLKDEV_INIT("31060000.ethernet", NULL, &clk_net), CLKDEV_INIT("dev:clcd", NULL, &clk_lcd), CLKDEV_INIT("31020000.usbd", "ck_usbd", &clk_usbd), + CLKDEV_INIT("31020000.ohci", "ck_usbd", &clk_usbd), + CLKDEV_INIT("31020000.usbd", "ck_usb_otg", &clk_usb_otg_dev), + CLKDEV_INIT("31020000.ohci", "ck_usb_otg", &clk_usb_otg_host), CLKDEV_INIT("lpc32xx_rtc", NULL, &clk_rtc), }; diff --git a/arch/arm/mach-lpc32xx/common.c b/arch/arm/mach-lpc32xx/common.c index 5c96057b6d78..a48dc2dec485 100644 --- a/arch/arm/mach-lpc32xx/common.c +++ b/arch/arm/mach-lpc32xx/common.c @@ -26,6 +26,7 @@ #include <linux/io.h> #include <asm/mach/map.h> +#include <asm/system_info.h> #include <mach/hardware.h> #include <mach/platform.h> @@ -224,7 +225,7 @@ void lpc23xx_restart(char mode, const char *cmd) ; } -static int __init lpc32xx_display_uid(void) +static int __init lpc32xx_check_uid(void) { u32 uid[4]; @@ -233,6 +234,11 @@ static int __init lpc32xx_display_uid(void) printk(KERN_INFO "LPC32XX unique ID: %08x%08x%08x%08x\n", uid[3], uid[2], uid[1], uid[0]); + if (!system_serial_low && !system_serial_high) { + system_serial_low = uid[0]; + system_serial_high = uid[1]; + } + return 1; } -arch_initcall(lpc32xx_display_uid); +arch_initcall(lpc32xx_check_uid); diff --git a/arch/arm/mach-lpc32xx/include/mach/gpio.h b/arch/arm/mach-lpc32xx/include/mach/gpio.h index 2ba6ca412bef..0052e7a76179 100644 --- a/arch/arm/mach-lpc32xx/include/mach/gpio.h +++ b/arch/arm/mach-lpc32xx/include/mach/gpio.h @@ -3,6 +3,4 @@ #include "gpio-lpc32xx.h" -#define ARCH_NR_GPIOS (LPC32XX_GPO_P3_GRP + LPC32XX_GPO_P3_MAX) - #endif /* __MACH_GPIO_H */ diff --git a/arch/arm/mach-lpc32xx/include/mach/platform.h b/arch/arm/mach-lpc32xx/include/mach/platform.h index c584f5bb164f..acc4aabf1c7b 100644 --- a/arch/arm/mach-lpc32xx/include/mach/platform.h +++ b/arch/arm/mach-lpc32xx/include/mach/platform.h @@ -694,4 +694,18 @@ #define LPC32XX_GPIO_P2_MUX_CLR _GPREG(0x02C) #define LPC32XX_GPIO_P2_MUX_STATE _GPREG(0x030) +/* + * USB Otg Registers + */ +#define _OTGREG(x) io_p2v(LPC32XX_USB_OTG_BASE + (x)) +#define LPC32XX_USB_OTG_CLK_CTRL _OTGREG(0xFF4) +#define LPC32XX_USB_OTG_CLK_STAT _OTGREG(0xFF8) + +/* USB OTG CLK CTRL bit defines */ +#define LPC32XX_USB_OTG_AHB_M_CLOCK_ON _BIT(4) +#define LPC32XX_USB_OTG_OTG_CLOCK_ON _BIT(3) +#define LPC32XX_USB_OTG_I2C_CLOCK_ON _BIT(2) +#define LPC32XX_USB_OTG_DEV_CLOCK_ON _BIT(1) +#define LPC32XX_USB_OTG_HOST_CLOCK_ON _BIT(0) + #endif diff --git a/arch/arm/mach-lpc32xx/phy3250.c b/arch/arm/mach-lpc32xx/phy3250.c index 540106cdb9ec..b07dcc90829d 100644 --- a/arch/arm/mach-lpc32xx/phy3250.c +++ b/arch/arm/mach-lpc32xx/phy3250.c @@ -30,12 +30,13 @@ #include <linux/amba/bus.h> #include <linux/amba/clcd.h> #include <linux/amba/pl022.h> +#include <linux/amba/pl08x.h> +#include <linux/amba/mmci.h> #include <linux/of.h> #include <linux/of_address.h> #include <linux/of_irq.h> #include <linux/of_platform.h> #include <linux/clk.h> -#include <linux/amba/pl08x.h> #include <asm/setup.h> #include <asm/mach-types.h> @@ -50,9 +51,9 @@ /* * Mapped GPIOLIB GPIOs */ -#define SPI0_CS_GPIO LPC32XX_GPIO(LPC32XX_GPIO_P3_GRP, 5) -#define LCD_POWER_GPIO LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 0) -#define BKL_POWER_GPIO LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 4) +#define LCD_POWER_GPIO LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 0) +#define BKL_POWER_GPIO LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 4) +#define MMC_PWR_ENABLE_GPIO LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 5) /* * AMBA LCD controller @@ -158,24 +159,6 @@ static struct clcd_board lpc32xx_clcd_data = { /* * AMBA SSP (SPI) */ -static void phy3250_spi_cs_set(u32 control) -{ - gpio_set_value(SPI0_CS_GPIO, (int) control); -} - -static struct pl022_config_chip spi0_chip_info = { - .com_mode = INTERRUPT_TRANSFER, - .iface = SSP_INTERFACE_MOTOROLA_SPI, - .hierarchy = SSP_MASTER, - .slave_tx_disable = 0, - .rx_lev_trig = SSP_RX_4_OR_MORE_ELEM, - .tx_lev_trig = SSP_TX_4_OR_MORE_EMPTY_LOC, - .ctrl_len = SSP_BITS_8, - .wait_state = SSP_MWIRE_WAIT_ZERO, - .duplex = SSP_MICROWIRE_CHANNEL_FULL_DUPLEX, - .cs_control = phy3250_spi_cs_set, -}; - static struct pl022_ssp_controller lpc32xx_ssp0_data = { .bus_id = 0, .num_chipselect = 1, @@ -188,45 +171,56 @@ static struct pl022_ssp_controller lpc32xx_ssp1_data = { .enable_dma = 0, }; -/* AT25 driver registration */ -static int __init phy3250_spi_board_register(void) +static struct pl08x_channel_data pl08x_slave_channels[] = { + { + .bus_id = "nand-slc", + .min_signal = 1, /* SLC NAND Flash */ + .max_signal = 1, + .periph_buses = PL08X_AHB1, + }, + { + .bus_id = "nand-mlc", + .min_signal = 12, /* MLC NAND Flash */ + .max_signal = 12, + .periph_buses = PL08X_AHB1, + }, +}; + +static int pl08x_get_signal(const struct pl08x_channel_data *cd) +{ + return cd->min_signal; +} + +static void pl08x_put_signal(const struct pl08x_channel_data *cd, int ch) { -#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE) - static struct spi_board_info info[] = { - { - .modalias = "spidev", - .max_speed_hz = 5000000, - .bus_num = 0, - .chip_select = 0, - .controller_data = &spi0_chip_info, - }, - }; - -#else - static struct spi_eeprom eeprom = { - .name = "at25256a", - .byte_len = 0x8000, - .page_size = 64, - .flags = EE_ADDR2, - }; - - static struct spi_board_info info[] = { - { - .modalias = "at25", - .max_speed_hz = 5000000, - .bus_num = 0, - .chip_select = 0, - .mode = SPI_MODE_0, - .platform_data = &eeprom, - .controller_data = &spi0_chip_info, - }, - }; -#endif - return spi_register_board_info(info, ARRAY_SIZE(info)); } -arch_initcall(phy3250_spi_board_register); static struct pl08x_platform_data pl08x_pd = { + .slave_channels = &pl08x_slave_channels[0], + .num_slave_channels = ARRAY_SIZE(pl08x_slave_channels), + .get_signal = pl08x_get_signal, + .put_signal = pl08x_put_signal, + .lli_buses = PL08X_AHB1, + .mem_buses = PL08X_AHB1, +}; + +static int mmc_handle_ios(struct device *dev, struct mmc_ios *ios) +{ + /* Only on and off are supported */ + if (ios->power_mode == MMC_POWER_OFF) + gpio_set_value(MMC_PWR_ENABLE_GPIO, 0); + else + gpio_set_value(MMC_PWR_ENABLE_GPIO, 1); + return 0; +} + +static struct mmci_platform_data lpc32xx_mmci_data = { + .ocr_mask = MMC_VDD_30_31 | MMC_VDD_31_32 | + MMC_VDD_32_33 | MMC_VDD_33_34, + .ios_handler = mmc_handle_ios, + .dma_filter = NULL, + /* No DMA for now since AMBA PL080 dmaengine driver only does scatter + * gather, and the MMCI driver doesn't do it this way */ }; static const struct of_dev_auxdata lpc32xx_auxdata_lookup[] __initconst = { @@ -234,6 +228,8 @@ static const struct of_dev_auxdata lpc32xx_auxdata_lookup[] __initconst = { OF_DEV_AUXDATA("arm,pl022", 0x2008C000, "dev:ssp1", &lpc32xx_ssp1_data), OF_DEV_AUXDATA("arm,pl110", 0x31040000, "dev:clcd", &lpc32xx_clcd_data), OF_DEV_AUXDATA("arm,pl080", 0x31000000, "pl08xdmac", &pl08x_pd), + OF_DEV_AUXDATA("arm,pl18x", 0x20098000, "20098000.sd", + &lpc32xx_mmci_data), { } }; @@ -241,10 +237,6 @@ static void __init lpc3250_machine_init(void) { u32 tmp; - /* Setup SLC NAND controller muxing */ - __raw_writel(LPC32XX_CLKPWR_NANDCLK_SEL_SLC, - LPC32XX_CLKPWR_NAND_CLK_CTRL); - /* Setup LCD muxing to RGB565 */ tmp = __raw_readl(LPC32XX_CLKPWR_LCDCLK_CTRL) & ~(LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_MSK | @@ -252,47 +244,8 @@ static void __init lpc3250_machine_init(void) tmp |= LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_TFT16; __raw_writel(tmp, LPC32XX_CLKPWR_LCDCLK_CTRL); - /* Set up USB power */ - tmp = __raw_readl(LPC32XX_CLKPWR_USB_CTRL); - tmp |= LPC32XX_CLKPWR_USBCTRL_HCLK_EN | - LPC32XX_CLKPWR_USBCTRL_USBI2C_EN; - __raw_writel(tmp, LPC32XX_CLKPWR_USB_CTRL); - - /* Set up I2C pull levels */ - tmp = __raw_readl(LPC32XX_CLKPWR_I2C_CLK_CTRL); - tmp |= LPC32XX_CLKPWR_I2CCLK_USBI2CHI_DRIVE | - LPC32XX_CLKPWR_I2CCLK_I2C2HI_DRIVE; - __raw_writel(tmp, LPC32XX_CLKPWR_I2C_CLK_CTRL); - - /* Disable IrDA pulsing support on UART6 */ - tmp = __raw_readl(LPC32XX_UARTCTL_CTRL); - tmp |= LPC32XX_UART_UART6_IRDAMOD_BYPASS; - __raw_writel(tmp, LPC32XX_UARTCTL_CTRL); - - /* Enable DMA for I2S1 channel */ - tmp = __raw_readl(LPC32XX_CLKPWR_I2S_CLK_CTRL); - tmp = LPC32XX_CLKPWR_I2SCTRL_I2S1_USE_DMA; - __raw_writel(tmp, LPC32XX_CLKPWR_I2S_CLK_CTRL); - lpc32xx_serial_init(); - /* - * AMBA peripheral clocks need to be enabled prior to AMBA device - * detection or a data fault will occur, so enable the clocks - * here. - */ - tmp = __raw_readl(LPC32XX_CLKPWR_LCDCLK_CTRL); - __raw_writel((tmp | LPC32XX_CLKPWR_LCDCTRL_CLK_EN), - LPC32XX_CLKPWR_LCDCLK_CTRL); - - tmp = __raw_readl(LPC32XX_CLKPWR_SSP_CLK_CTRL); - __raw_writel((tmp | LPC32XX_CLKPWR_SSPCTRL_SSPCLK0_EN), - LPC32XX_CLKPWR_SSP_CLK_CTRL); - - tmp = __raw_readl(LPC32XX_CLKPWR_DMA_CLK_CTRL); - __raw_writel((tmp | LPC32XX_CLKPWR_DMACLKCTRL_CLK_EN), - LPC32XX_CLKPWR_DMA_CLK_CTRL); - /* Test clock needed for UDA1380 initial init */ __raw_writel(LPC32XX_CLKPWR_TESTCLK2_SEL_MOSC | LPC32XX_CLKPWR_TESTCLK_TESTCLK2_EN, @@ -302,12 +255,10 @@ static void __init lpc3250_machine_init(void) lpc32xx_auxdata_lookup, NULL); /* Register GPIOs used on this board */ - if (gpio_request(SPI0_CS_GPIO, "spi0 cs")) - printk(KERN_ERR "Error requesting gpio %u", - SPI0_CS_GPIO); - else if (gpio_direction_output(SPI0_CS_GPIO, 1)) - printk(KERN_ERR "Error setting gpio %u to output", - SPI0_CS_GPIO); + if (gpio_request(MMC_PWR_ENABLE_GPIO, "mmc_power_en")) + pr_err("Error requesting gpio %u", MMC_PWR_ENABLE_GPIO); + else if (gpio_direction_output(MMC_PWR_ENABLE_GPIO, 1)) + pr_err("Error setting gpio %u to output", MMC_PWR_ENABLE_GPIO); } static char const *lpc32xx_dt_compat[] __initdata = { diff --git a/arch/arm/mach-lpc32xx/serial.c b/arch/arm/mach-lpc32xx/serial.c index f2735281616a..05621a29fba2 100644 --- a/arch/arm/mach-lpc32xx/serial.c +++ b/arch/arm/mach-lpc32xx/serial.c @@ -31,59 +31,6 @@ #define LPC32XX_SUART_FIFO_SIZE 64 -/* Standard 8250/16550 compatible serial ports */ -static struct plat_serial8250_port serial_std_platform_data[] = { -#ifdef CONFIG_ARCH_LPC32XX_UART5_SELECT - { - .membase = io_p2v(LPC32XX_UART5_BASE), - .mapbase = LPC32XX_UART5_BASE, - .irq = IRQ_LPC32XX_UART_IIR5, - .uartclk = LPC32XX_MAIN_OSC_FREQ, - .regshift = 2, - .iotype = UPIO_MEM32, - .flags = UPF_BOOT_AUTOCONF | UPF_BUGGY_UART | - UPF_SKIP_TEST, - }, -#endif -#ifdef CONFIG_ARCH_LPC32XX_UART3_SELECT - { - .membase = io_p2v(LPC32XX_UART3_BASE), - .mapbase = LPC32XX_UART3_BASE, - .irq = IRQ_LPC32XX_UART_IIR3, - .uartclk = LPC32XX_MAIN_OSC_FREQ, - .regshift = 2, - .iotype = UPIO_MEM32, - .flags = UPF_BOOT_AUTOCONF | UPF_BUGGY_UART | - UPF_SKIP_TEST, - }, -#endif -#ifdef CONFIG_ARCH_LPC32XX_UART4_SELECT - { - .membase = io_p2v(LPC32XX_UART4_BASE), - .mapbase = LPC32XX_UART4_BASE, - .irq = IRQ_LPC32XX_UART_IIR4, - .uartclk = LPC32XX_MAIN_OSC_FREQ, - .regshift = 2, - .iotype = UPIO_MEM32, - .flags = UPF_BOOT_AUTOCONF | UPF_BUGGY_UART | - UPF_SKIP_TEST, - }, -#endif -#ifdef CONFIG_ARCH_LPC32XX_UART6_SELECT - { - .membase = io_p2v(LPC32XX_UART6_BASE), - .mapbase = LPC32XX_UART6_BASE, - .irq = IRQ_LPC32XX_UART_IIR6, - .uartclk = LPC32XX_MAIN_OSC_FREQ, - .regshift = 2, - .iotype = UPIO_MEM32, - .flags = UPF_BOOT_AUTOCONF | UPF_BUGGY_UART | - UPF_SKIP_TEST, - }, -#endif - { }, -}; - struct uartinit { char *uart_ck_name; u32 ck_mode_mask; @@ -92,7 +39,6 @@ struct uartinit { }; static struct uartinit uartinit_data[] __initdata = { -#ifdef CONFIG_ARCH_LPC32XX_UART5_SELECT { .uart_ck_name = "uart5_ck", .ck_mode_mask = @@ -100,8 +46,6 @@ static struct uartinit uartinit_data[] __initdata = { .pdiv_clk_reg = LPC32XX_CLKPWR_UART5_CLK_CTRL, .mapbase = LPC32XX_UART5_BASE, }, -#endif -#ifdef CONFIG_ARCH_LPC32XX_UART3_SELECT { .uart_ck_name = "uart3_ck", .ck_mode_mask = @@ -109,8 +53,6 @@ static struct uartinit uartinit_data[] __initdata = { .pdiv_clk_reg = LPC32XX_CLKPWR_UART3_CLK_CTRL, .mapbase = LPC32XX_UART3_BASE, }, -#endif -#ifdef CONFIG_ARCH_LPC32XX_UART4_SELECT { .uart_ck_name = "uart4_ck", .ck_mode_mask = @@ -118,8 +60,6 @@ static struct uartinit uartinit_data[] __initdata = { .pdiv_clk_reg = LPC32XX_CLKPWR_UART4_CLK_CTRL, .mapbase = LPC32XX_UART4_BASE, }, -#endif -#ifdef CONFIG_ARCH_LPC32XX_UART6_SELECT { .uart_ck_name = "uart6_ck", .ck_mode_mask = @@ -127,19 +67,6 @@ static struct uartinit uartinit_data[] __initdata = { .pdiv_clk_reg = LPC32XX_CLKPWR_UART6_CLK_CTRL, .mapbase = LPC32XX_UART6_BASE, }, -#endif -}; - -static struct platform_device serial_std_platform_device = { - .name = "serial8250", - .id = 0, - .dev = { - .platform_data = serial_std_platform_data, - }, -}; - -static struct platform_device *lpc32xx_serial_devs[] __initdata = { - &serial_std_platform_device, }; void __init lpc32xx_serial_init(void) @@ -156,15 +83,8 @@ void __init lpc32xx_serial_init(void) clk = clk_get(NULL, uartinit_data[i].uart_ck_name); if (!IS_ERR(clk)) { clk_enable(clk); - serial_std_platform_data[i].uartclk = - clk_get_rate(clk); } - /* Fall back on main osc rate if clock rate return fails */ - if (serial_std_platform_data[i].uartclk == 0) - serial_std_platform_data[i].uartclk = - LPC32XX_MAIN_OSC_FREQ; - /* Setup UART clock modes for all UARTs, disable autoclock */ clkmodes |= uartinit_data[i].ck_mode_mask; @@ -189,7 +109,7 @@ void __init lpc32xx_serial_init(void) __raw_writel(clkmodes, LPC32XX_UARTCTL_CLKMODE); for (i = 0; i < ARRAY_SIZE(uartinit_data); i++) { /* Force a flush of the RX FIFOs to work around a HW bug */ - puart = serial_std_platform_data[i].mapbase; + puart = uartinit_data[i].mapbase; __raw_writel(0xC1, LPC32XX_UART_IIR_FCR(puart)); __raw_writel(0x00, LPC32XX_UART_DLL_FIFO(puart)); j = LPC32XX_SUART_FIFO_SIZE; @@ -198,11 +118,13 @@ void __init lpc32xx_serial_init(void) __raw_writel(0, LPC32XX_UART_IIR_FCR(puart)); } + /* Disable IrDA pulsing support on UART6 */ + tmp = __raw_readl(LPC32XX_UARTCTL_CTRL); + tmp |= LPC32XX_UART_UART6_IRDAMOD_BYPASS; + __raw_writel(tmp, LPC32XX_UARTCTL_CTRL); + /* Disable UART5->USB transparent mode or USB won't work */ tmp = __raw_readl(LPC32XX_UARTCTL_CTRL); tmp &= ~LPC32XX_UART_U5_ROUTE_TO_USB; __raw_writel(tmp, LPC32XX_UARTCTL_CTRL); - - platform_add_devices(lpc32xx_serial_devs, - ARRAY_SIZE(lpc32xx_serial_devs)); } |