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authorHonghui Zhang <honghui.zhang@mediatek.com>2016-08-11 16:07:08 +0800
committerJoerg Roedel <jroedel@suse.de>2016-08-22 12:52:10 +0200
commit615cca8c0c2245e7e8c1b1986071506807cbfa90 (patch)
tree4dffc1cd85fabd19a4ee9b5d8a83d17e1faed77e /include/dt-bindings/memory
parentfa8410b355251fd30341662a40ac6b22d3e38468 (diff)
iommu/mediatek: dt-binding: Correct the larb port offset defines for mt2701
larb2 have 23 ports, the LARB3_PORT_OFFSET should be LARB2_PORT_OFFSET plus larb2's port number, it should be 44 instead of 43. Signed-off-by: Honghui Zhang <honghui.zhang@mediatek.com> Signed-off-by: Joerg Roedel <jroedel@suse.de>
Diffstat (limited to 'include/dt-bindings/memory')
-rw-r--r--include/dt-bindings/memory/mt2701-larb-port.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/include/dt-bindings/memory/mt2701-larb-port.h b/include/dt-bindings/memory/mt2701-larb-port.h
index 78f66786da91..6764d7447422 100644
--- a/include/dt-bindings/memory/mt2701-larb-port.h
+++ b/include/dt-bindings/memory/mt2701-larb-port.h
@@ -26,7 +26,7 @@
#define LARB0_PORT_OFFSET 0
#define LARB1_PORT_OFFSET 11
#define LARB2_PORT_OFFSET 21
-#define LARB3_PORT_OFFSET 43
+#define LARB3_PORT_OFFSET 44
#define MT2701_M4U_ID_LARB0(port) ((port) + LARB0_PORT_OFFSET)
#define MT2701_M4U_ID_LARB1(port) ((port) + LARB1_PORT_OFFSET)