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authorShaik Ameer Basha <shaik.ameer@samsung.com>2014-05-08 16:57:57 +0530
committerTomasz Figa <t.figa@samsung.com>2014-05-14 19:40:20 +0200
commit0a22c3065333d3138475ff1d25851633e8dae722 (patch)
tree38665d666474c7c5e422731d13daa10b0c4bf256 /include/dt-bindings/clock
parentfaec151b5006f832c8cefc76d01893496445a7ec (diff)
clk: samsung: exynos5420: update clocks for PERIS and GEN blocks
This patch fixes some parent-child relationships according to the latest datasheet and adds more clocks related to PERIS and GEN blocks. Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com> Signed-off-by: Shaik Ameer Basha <shaik.ameer@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Diffstat (limited to 'include/dt-bindings/clock')
-rw-r--r--include/dt-bindings/clock/exynos5420.h3
1 files changed, 3 insertions, 0 deletions
diff --git a/include/dt-bindings/clock/exynos5420.h b/include/dt-bindings/clock/exynos5420.h
index e688b64564b2..16262da05cf2 100644
--- a/include/dt-bindings/clock/exynos5420.h
+++ b/include/dt-bindings/clock/exynos5420.h
@@ -153,6 +153,7 @@
#define CLK_JPEG 451
#define CLK_JPEG2 452
#define CLK_SMMU_JPEG 453
+#define CLK_SMMU_JPEG2 454
#define CLK_ACLK300_GSCL 460
#define CLK_SMMU_GSCL0 461
#define CLK_SMMU_GSCL1 462
@@ -180,6 +181,8 @@
#define CLK_SMMU_MIXER 502
#define CLK_SMMU_G2D 503
#define CLK_SMMU_MDMA0 504
+#define CLK_MC 505
+#define CLK_TOP_RTC 506
#define CLK_SCLK_UART_ISP 510
#define CLK_SCLK_SPI0_ISP 511
#define CLK_SCLK_SPI1_ISP 512