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authorLinus Torvalds <torvalds@g5.osdl.org>2005-10-29 12:19:15 -0700
committerLinus Torvalds <torvalds@g5.osdl.org>2005-10-29 12:19:15 -0700
commite9d52234e35b27ea4ea5f2ab64ca47b1a0c740ab (patch)
tree318d37a7d55c79e6f7d86163fb28e0eccbb0fe83 /include/asm-mips/mach-pnx8550/cm.h
parent955c5038823748e529a49f0e33ab635d92843500 (diff)
parent09af7b443c257460d45cb6c1896d29f173fef35b (diff)
Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus
Diffstat (limited to 'include/asm-mips/mach-pnx8550/cm.h')
-rw-r--r--include/asm-mips/mach-pnx8550/cm.h43
1 files changed, 43 insertions, 0 deletions
diff --git a/include/asm-mips/mach-pnx8550/cm.h b/include/asm-mips/mach-pnx8550/cm.h
new file mode 100644
index 000000000000..bb0a56c7d011
--- /dev/null
+++ b/include/asm-mips/mach-pnx8550/cm.h
@@ -0,0 +1,43 @@
+/*
+ *
+ * BRIEF MODULE DESCRIPTION
+ * Clock module specific definitions
+ *
+ * Author: source@mvista.com
+ *
+ * This program is free software; you can distribute it and/or modify it
+ * under the terms of the GNU General Public License (Version 2) as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ */
+
+#ifndef __PNX8550_CM_H
+#define __PNX8550_CM_H
+
+#define PNX8550_CM_BASE 0xBBE47000
+
+#define PNX8550_CM_PLL0_CTL *(volatile unsigned long *)(PNX8550_CM_BASE + 0x000)
+#define PNX8550_CM_PLL1_CTL *(volatile unsigned long *)(PNX8550_CM_BASE + 0x004)
+#define PNX8550_CM_PLL2_CTL *(volatile unsigned long *)(PNX8550_CM_BASE + 0x008)
+#define PNX8550_CM_PLL3_CTL *(volatile unsigned long *)(PNX8550_CM_BASE + 0x00C)
+
+// Table not complete.....
+
+#define PNX8550_CM_PLL_BLOCKED_MASK 0x80000000
+#define PNX8550_CM_PLL_LOCK_MASK 0x40000000
+#define PNX8550_CM_PLL_CURRENT_ADJ_MASK 0x3c000000
+#define PNX8550_CM_PLL_N_MASK 0x01ff0000
+#define PNX8550_CM_PLL_M_MASK 0x00003f00
+#define PNX8550_CM_PLL_P_MASK 0x0000000c
+#define PNX8550_CM_PLL_PD_MASK 0x00000002
+
+
+#endif