diff options
| author | Dong Aisheng <aisheng.dong@nxp.com> | 2017-05-19 15:05:43 +0800 |
|---|---|---|
| committer | Linus Walleij <linus.walleij@linaro.org> | 2017-05-22 11:05:19 +0200 |
| commit | 5586ee4191219f74632ad6e527c46d1c3d9cdf3e (patch) | |
| tree | d96338efd6ffa2f91556f2195cb357212e93d557 /drivers/pinctrl/freescale/pinctrl-imx.c | |
| parent | a5cadbbb081cb84a9fdb14391fb461a41f089a0a (diff) | |
pinctrl: imx: add soc specific mux_mode mask and shift property
MX7ULP MUX mode mask and shift bit is different from VF610.
Let's make it a platform specific property for the later easy of
adding MX7ULP support.
One trick in exist code that Vybrid hardcoded the config part
as 0xffff because its mux_config register BIT[15-0] are all configs
part. But it's not true in ULP, so use mux_mask instead to address
the difference.
Cc: Stefan Agner <stefan@agner.ch>
Cc: Bai Ping <ping.bai@nxp.com>
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Acked-by: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'drivers/pinctrl/freescale/pinctrl-imx.c')
| -rw-r--r-- | drivers/pinctrl/freescale/pinctrl-imx.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/drivers/pinctrl/freescale/pinctrl-imx.c b/drivers/pinctrl/freescale/pinctrl-imx.c index 328d079b237e..72aca758f4c6 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx.c +++ b/drivers/pinctrl/freescale/pinctrl-imx.c @@ -197,8 +197,8 @@ static int imx_pmx_set(struct pinctrl_dev *pctldev, unsigned selector, if (info->flags & SHARE_MUX_CONF_REG) { u32 reg; reg = readl(ipctl->base + pin_reg->mux_reg); - reg &= ~(0x7 << 20); - reg |= (pin->mux_mode << 20); + reg &= ~info->mux_mask; + reg |= (pin->mux_mode << info->mux_shift); writel(reg, ipctl->base + pin_reg->mux_reg); dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n", pin_reg->mux_reg, reg); @@ -290,7 +290,7 @@ static int imx_pmx_gpio_request_enable(struct pinctrl_dev *pctldev, mux_pin: reg = readl(ipctl->base + pin_reg->mux_reg); - reg &= ~(0x7 << 20); + reg &= ~info->mux_mask; reg |= imx_pin->config; writel(reg, ipctl->base + pin_reg->mux_reg); @@ -434,7 +434,7 @@ static int imx_pinconf_get(struct pinctrl_dev *pctldev, *config = readl(ipctl->base + pin_reg->conf_reg); if (info->flags & SHARE_MUX_CONF_REG) - *config &= 0xffff; + *config &= ~info->mux_mask; return 0; } @@ -461,7 +461,7 @@ static int imx_pinconf_set(struct pinctrl_dev *pctldev, if (info->flags & SHARE_MUX_CONF_REG) { u32 reg; reg = readl(ipctl->base + pin_reg->conf_reg); - reg &= ~0xffff; + reg &= info->mux_mask; reg |= configs[i]; writel(reg, ipctl->base + pin_reg->conf_reg); dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n", |