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authorYang Wang <kevinyang.wang@amd.com>2024-04-23 10:14:47 +0800
committerAlex Deucher <alexander.deucher@amd.com>2024-04-30 09:58:47 -0400
commit5eccab32c15f1e5cf9651d865fb20012d3563c96 (patch)
tree1c86a224e822846f03f38b13ba048367ff6fa3ec /drivers/gpu/drm/amd/amdgpu/amdgpu_mca.h
parent76ad30f51aa0d1bd99f12658d4775a86df6e4282 (diff)
drm/amdgpu: avoid dump mca bank log muti times during ras ISR
because the ue valid mca count will only be cleared after gpu reset, so only dump mca log on the first time to get mca bank after receive RAS interrupt. Signed-off-by: Yang Wang <kevinyang.wang@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_mca.h')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_mca.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mca.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mca.h
index 9b97cfa28e05..e80323ff90c1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mca.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mca.h
@@ -93,6 +93,7 @@ struct amdgpu_mca {
struct amdgpu_mca_ras mpio;
const struct amdgpu_mca_smu_funcs *mca_funcs;
struct mca_bank_cache mca_caches[AMDGPU_MCA_ERROR_TYPE_DE];
+ atomic_t ue_update_flag;
};
enum mca_reg_idx {