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authorChang Rebecca Swee Fun <rebecca.swee.fun.chang@intel.com>2014-12-08 17:38:10 +0800
committerLinus Walleij <linus.walleij@linaro.org>2015-01-15 17:23:12 +0100
commit920214902502ceb0445a25b530dfe4c465cf8575 (patch)
treeb65a1c9adfc8ed1641a73c9f9def2f34e348b278 /drivers/gpio/gpio-sch.c
parentae9ca493ee2adaebc2bccd60fb6ccf93a214262c (diff)
gpio: sch: Add support for Intel Quark X1000 SoC
Intel Quark X1000 provides a total of 16 GPIOs. The GPIOs are split between the legacy I/O bridge and the GPIO controller. GPIO-SCH is the GPIO pins on legacy bridge for Intel Quark SoC. Intel Quark X1000 has 2 GPIOs powered by the core power well and 6 from the suspend power well. This piece of work is derived from Dan O'Donovan's initial work for Quark X1000 enabling. Signed-off-by: Chang Rebecca Swee Fun <rebecca.swee.fun.chang@intel.com> Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com> Reviewed-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'drivers/gpio/gpio-sch.c')
-rw-r--r--drivers/gpio/gpio-sch.c6
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/gpio/gpio-sch.c b/drivers/gpio/gpio-sch.c
index 0a0cf1307d2f..0271022a66f6 100644
--- a/drivers/gpio/gpio-sch.c
+++ b/drivers/gpio/gpio-sch.c
@@ -230,6 +230,12 @@ static int sch_gpio_probe(struct platform_device *pdev)
sch->chip.ngpio = 30;
break;
+ case PCI_DEVICE_ID_INTEL_QUARK_X1000_ILB:
+ sch->core_base = 0;
+ sch->resume_base = 2;
+ sch->chip.ngpio = 8;
+ break;
+
default:
return -ENODEV;
}