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authorMaxime Ripard <maxime.ripard@free-electrons.com>2017-01-19 22:49:26 +0100
committerMaxime Ripard <maxime.ripard@free-electrons.com>2017-01-23 11:45:02 +0100
commit7c09b858961df25a3bd1ac22e802525795338a6d (patch)
tree725afd33be597d655533de50cb85f377a45af4af /drivers/clk
parent0c3c8e135897eb8e896a0bb82a5aff6c9bc158cc (diff)
clk: sunxi-ng: Implement global pre-divider
Some clocks have a global pre-divider that applies to all their parents. Since it might also apply to clocks that have a single parent, this is merged in the ccu_common structure, unlike the other pre-divider settings that are tied to a specific index, and thus a specific parent. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Diffstat (limited to 'drivers/clk')
-rw-r--r--drivers/clk/sunxi-ng/ccu_common.h2
-rw-r--r--drivers/clk/sunxi-ng/ccu_mux.c8
2 files changed, 9 insertions, 1 deletions
diff --git a/drivers/clk/sunxi-ng/ccu_common.h b/drivers/clk/sunxi-ng/ccu_common.h
index b3d9abfbd721..cdd69eb2e0b9 100644
--- a/drivers/clk/sunxi-ng/ccu_common.h
+++ b/drivers/clk/sunxi-ng/ccu_common.h
@@ -21,6 +21,7 @@
#define CCU_FEATURE_VARIABLE_PREDIV BIT(1)
#define CCU_FEATURE_FIXED_PREDIV BIT(2)
#define CCU_FEATURE_FIXED_POSTDIV BIT(3)
+#define CCU_FEATURE_ALL_PREDIV BIT(4)
struct device_node;
@@ -56,6 +57,7 @@ struct device_node;
struct ccu_common {
void __iomem *base;
u16 reg;
+ u32 prediv;
unsigned long features;
spinlock_t *lock;
diff --git a/drivers/clk/sunxi-ng/ccu_mux.c b/drivers/clk/sunxi-ng/ccu_mux.c
index a43ad52a957d..858a48621631 100644
--- a/drivers/clk/sunxi-ng/ccu_mux.c
+++ b/drivers/clk/sunxi-ng/ccu_mux.c
@@ -25,9 +25,15 @@ void ccu_mux_helper_adjust_parent_for_prediv(struct ccu_common *common,
int i;
if (!((common->features & CCU_FEATURE_FIXED_PREDIV) ||
- (common->features & CCU_FEATURE_VARIABLE_PREDIV)))
+ (common->features & CCU_FEATURE_VARIABLE_PREDIV) ||
+ (common->features & CCU_FEATURE_ALL_PREDIV)))
return;
+ if (common->features & CCU_FEATURE_ALL_PREDIV) {
+ *parent_rate = *parent_rate / common->prediv;
+ return;
+ }
+
reg = readl(common->base + common->reg);
if (parent_index < 0) {
parent_index = reg >> cm->shift;