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authorUlf Hansson <ulf.hansson@linaro.org>2012-09-24 16:43:18 +0200
committerMike Turquette <mturquette@linaro.org>2012-10-29 11:05:53 -0700
commitb0ea0fc753bfda1e9c20af403187758eb32052fd (patch)
tree24bd94fd8c5afdf63b1b2792621cbdea1b6e4438 /drivers/clk/ux500/clk.h
parent686f871b7109e7e253a7a1cef542c00d0ed1a323 (diff)
clk: ux500: Support prcmu ape opp voltage clock
Some scalable prcmu clocks needs to be handled in conjuction with the ape opp 100 voltage. A new prcmu clock type clk_prcmu_opp_volt_scalable is implemented to handle this. Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
Diffstat (limited to 'drivers/clk/ux500/clk.h')
-rw-r--r--drivers/clk/ux500/clk.h6
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/clk/ux500/clk.h b/drivers/clk/ux500/clk.h
index 836d7d16751e..f36eeedca493 100644
--- a/drivers/clk/ux500/clk.h
+++ b/drivers/clk/ux500/clk.h
@@ -45,4 +45,10 @@ struct clk *clk_reg_prcmu_opp_gate(const char *name,
u8 cg_sel,
unsigned long flags);
+struct clk *clk_reg_prcmu_opp_volt_scalable(const char *name,
+ const char *parent_name,
+ u8 cg_sel,
+ unsigned long rate,
+ unsigned long flags);
+
#endif /* __UX500_CLK_H */