diff options
| author | Katsuhiro Suzuki <suzuki.katsuhiro@socionext.com> | 2017-08-10 16:23:46 +0900 |
|---|---|---|
| committer | Stephen Boyd <sboyd@codeaurora.org> | 2017-08-31 18:41:14 -0700 |
| commit | 6c264416c9b3dfd860aba9bcbe0ab4e0f061c0ca (patch) | |
| tree | d6a6b3c59026a111db12c50db281d3a9e6c772e4 /drivers/clk/uniphier | |
| parent | e3dd205860a52347a858db58ace3d28998105da1 (diff) | |
clk: uniphier: add video input subsystem clock
Add a clock for video input subsystem (EXIV) on
UniPhier LD11/LD20 SoCs.
Signed-off-by: Katsuhiro Suzuki <suzuki.katsuhiro@socionext.com>
Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'drivers/clk/uniphier')
| -rw-r--r-- | drivers/clk/uniphier/clk-uniphier-sys.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/clk/uniphier/clk-uniphier-sys.c b/drivers/clk/uniphier/clk-uniphier-sys.c index 52048696931d..0e396f3da526 100644 --- a/drivers/clk/uniphier/clk-uniphier-sys.c +++ b/drivers/clk/uniphier/clk-uniphier-sys.c @@ -65,6 +65,10 @@ UNIPHIER_CLK_FACTOR("evea-io100m", -1, "spll", 1, 20), \ UNIPHIER_CLK_GATE("evea", (idx), "evea-io100m", 0x2108, 1) +#define UNIPHIER_LD11_SYS_CLK_EXIV(idx) \ + UNIPHIER_CLK_FACTOR("exiv-io200m", -1, "spll", 1, 10), \ + UNIPHIER_CLK_GATE("exiv", (idx), "exiv-io200m", 0x2110, 2) + #define UNIPHIER_PRO4_SYS_CLK_ETHER(idx) \ UNIPHIER_CLK_GATE("ether", (idx), NULL, 0x2104, 12) @@ -163,6 +167,7 @@ const struct uniphier_clk_data uniphier_ld11_sys_clk_data[] = { UNIPHIER_CLK_FACTOR("usb2", -1, "ref", 24, 25), UNIPHIER_LD11_SYS_CLK_AIO(40), UNIPHIER_LD11_SYS_CLK_EVEA(41), + UNIPHIER_LD11_SYS_CLK_EXIV(42), /* CPU gears */ UNIPHIER_CLK_DIV4("cpll", 2, 3, 4, 8), UNIPHIER_CLK_DIV4("mpll", 2, 3, 4, 8), @@ -202,6 +207,7 @@ const struct uniphier_clk_data uniphier_ld20_sys_clk_data[] = { UNIPHIER_CLK_GATE("usb30-phy1", 17, NULL, 0x210c, 13), UNIPHIER_LD11_SYS_CLK_AIO(40), UNIPHIER_LD11_SYS_CLK_EVEA(41), + UNIPHIER_LD11_SYS_CLK_EXIV(42), /* CPU gears */ UNIPHIER_CLK_DIV4("cpll", 2, 3, 4, 8), UNIPHIER_CLK_DIV4("spll", 2, 3, 4, 8), |