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authorRobert Jarzmik <robert.jarzmik@free.fr>2016-10-23 14:19:27 +0200
committerStephen Boyd <sboyd@codeaurora.org>2016-11-01 17:46:49 -0700
commit26bd423b88a7a5c5fe5a042a8d7209d5ebdcbd1b (patch)
tree91559c72bcf75232a0714f9f816a6766d0d3eed4 /drivers/clk/pxa/clk-pxa25x.c
parent06b8ec4eadde7054528b779974ae5ff998c0b0a2 (diff)
clk: pxa: core pll is not affected by t bit
The t bit of clkfcfg doesn't affect the core pll clock, but it makes core clock select between core pll clock and core run clock. As such remove it from the core pll rate reporting function, while it remains in clk_pxa27x_core_get_parent(). Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'drivers/clk/pxa/clk-pxa25x.c')
-rw-r--r--drivers/clk/pxa/clk-pxa25x.c4
1 files changed, 1 insertions, 3 deletions
diff --git a/drivers/clk/pxa/clk-pxa25x.c b/drivers/clk/pxa/clk-pxa25x.c
index a98b98e2a9e4..3bb603a27f2b 100644
--- a/drivers/clk/pxa/clk-pxa25x.c
+++ b/drivers/clk/pxa/clk-pxa25x.c
@@ -182,9 +182,7 @@ static unsigned long clk_pxa25x_cpll_get_rate(struct clk_hw *hw,
m = M_clk_mult[(cccr >> 5) & 0x03];
n2 = N2_clk_mult[(cccr >> 7) & 0x07];
- if (t)
- return m * l * n2 * parent_rate / 2;
- return m * l * parent_rate;
+ return m * l * n2 * parent_rate / 2;
}
PARENTS(clk_pxa25x_cpll) = { "osc_3_6864mhz" };
RATE_RO_OPS(clk_pxa25x_cpll, "cpll");