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authorYuantian Tang <andy.tang@nxp.com>2017-04-06 10:21:23 +0800
committerStephen Boyd <sboyd@codeaurora.org>2017-07-21 15:01:45 -0700
commit45899dc5f1b5107903b2bc1c78e22d7945a895fd (patch)
tree3fd26f32e29df70988425286b55376755f755d33 /drivers/clk/mediatek
parente0c888c4a24dd4e55525f37ac854125b3e90c99a (diff)
clk: qoriq: add pll clock to clock lookup table
Register each PLL and its division clocks to clock lookup table to facilitate the clock look up for clock consumer. Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'drivers/clk/mediatek')
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