diff options
| author | Dave Airlie <airlied@gmail.com> | 2011-01-12 10:49:03 +1000 |
|---|---|---|
| committer | Dave Airlie <airlied@gmail.com> | 2011-01-12 10:49:03 +1000 |
| commit | 784fe39fa80d557847baeca2695915d17b09827f (patch) | |
| tree | a258083fb42459b6f5415e397c0ce551713fc1ed /drivers/char/agp/intel-agp.h | |
| parent | 4162cf64973df51fc885825bc9ca4d055891c49f (diff) | |
| parent | 6fe4f14044f181e146cdc15485428f95fa541ce8 (diff) | |
Merge branch 'drm-intel-fixes' of ssh://master.kernel.org/pub/scm/linux/kernel/git/ickle/drm-intel
* 'drm-intel-fixes' of ssh://master.kernel.org/pub/scm/linux/kernel/git/ickle/drm-intel: (37 commits)
drm/i915/execbuffer: Reorder binding of objects to favour restrictions
drm/i915: If we hit OOM when allocating GTT pages, clear the aperture
drm/i915/evict: Ensure we completely cleanup on failure
drm/i915/execbuffer: Correctly clear the current object list upon EFAULT
drm/i915/debugfs: Show all objects in the gtt
drm/i915: Record AGP memory type upon error
drm/i915: Periodically flush the active lists and requests
drm/i915/gtt: Unmap the PCI pages after unbinding them from the GTT
drm/i915: Record the error batchbuffer on each ring
drm/i915: Include TLB miss overhead for computing WM
drm/i915: Propagate error from flushing the ring
drm/i915: detect & report PCH display error interrupts
drm/i915: cleanup rc6 code
drm/i915: fix rc6 enabling around suspend/resume
drm/i915: re-enable rc6 support for Ironlake+
drm/i915: Make the ring IMR handling private
drm/i915/ringbuffer: Simplify the ring irq refcounting
drm/i915/debugfs: Show the per-ring IMR
drm/i915: Mask USER interrupts on gen6 (until required)
drm/i915: Handle ringbuffer stalls when flushing
...
Diffstat (limited to 'drivers/char/agp/intel-agp.h')
| -rw-r--r-- | drivers/char/agp/intel-agp.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/char/agp/intel-agp.h b/drivers/char/agp/intel-agp.h index 010e3defd6c3..c195bfeade11 100644 --- a/drivers/char/agp/intel-agp.h +++ b/drivers/char/agp/intel-agp.h @@ -94,6 +94,8 @@ #define G4x_GMCH_SIZE_VT_1_5M (0xa << 8) #define G4x_GMCH_SIZE_VT_2M (0xc << 8) +#define GFX_FLSH_CNTL 0x2170 /* 915+ */ + #define I810_DRAM_CTL 0x3000 #define I810_DRAM_ROW_0 0x00000001 #define I810_DRAM_ROW_0_SDRAM 0x00000001 |