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authorStephane Eranian <eranian@google.com>2010-02-08 17:17:01 +0200
committerIngo Molnar <mingo@elte.hu>2010-02-26 10:56:53 +0100
commit38331f62c20456454eed9ebea2525f072c6f1d2e (patch)
treea285f82e0f8a9c62305f8499f966a5ec5ae3671d /arch/sparc
parentd76a0812ac4139ceb54daab3cc70e1bd8bd9d43a (diff)
perf_events, x86: AMD event scheduling
This patch adds correct AMD NorthBridge event scheduling. NB events are events measuring L3 cache, Hypertransport traffic. They are identified by an event code >= 0xe0. They measure events on the Northbride which is shared by all cores on a package. NB events are counted on a shared set of counters. When a NB event is programmed in a counter, the data actually comes from a shared counter. Thus, access to those counters needs to be synchronized. We implement the synchronization such that no two cores can be measuring NB events using the same counters. Thus, we maintain a per-NB allocation table. The available slot is propagated using the event_constraint structure. Signed-off-by: Stephane Eranian <eranian@google.com> Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl> LKML-Reference: <4b703957.0702d00a.6bf2.7b7d@mx.google.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
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