diff options
| author | Gabor Juhos <juhosg@openwrt.org> | 2012-03-14 10:45:21 +0100 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2012-05-15 17:49:07 +0200 |
| commit | d84114660a65e89e27ebd3fb21ce71ff579ee882 (patch) | |
| tree | e73cace8d697ad2ad9304630414389c36fd18d29 /arch/mips/ath79 | |
| parent | 80a7ed81a840aee97f7650cbeaabb3c2c1765e70 (diff) | |
MIPS: ath79: add SoC detection code for AR934X
Also add 'soc_is_ar934[124x]' helper functions and a Kconfig
symbol for the AR934X SoCs.
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Acked-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com>
Cc: linux-mips@linux-mips.org
Cc: mcgrof@infradead.org
Patchwork: https://patchwork.linux-mips.org/patch/3506/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/ath79')
| -rw-r--r-- | arch/mips/ath79/Kconfig | 4 | ||||
| -rw-r--r-- | arch/mips/ath79/setup.c | 21 |
2 files changed, 24 insertions, 1 deletions
diff --git a/arch/mips/ath79/Kconfig b/arch/mips/ath79/Kconfig index bc6edada38ac..7db8e8903a7b 100644 --- a/arch/mips/ath79/Kconfig +++ b/arch/mips/ath79/Kconfig @@ -69,6 +69,10 @@ config SOC_AR933X select USB_ARCH_HAS_EHCI def_bool n +config SOC_AR934X + select USB_ARCH_HAS_EHCI + def_bool n + config ATH79_DEV_GPIO_BUTTONS def_bool n diff --git a/arch/mips/ath79/setup.c b/arch/mips/ath79/setup.c index 24dfedfb1740..60d212ef8629 100644 --- a/arch/mips/ath79/setup.c +++ b/arch/mips/ath79/setup.c @@ -1,10 +1,11 @@ /* * Atheros AR71XX/AR724X/AR913X specific setup * + * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com> * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org> * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> * - * Parts of this file are based on Atheros' 2.6.15 BSP + * Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License version 2 as published @@ -145,6 +146,24 @@ static void __init ath79_detect_sys_type(void) rev = id & AR933X_REV_ID_REVISION_MASK; break; + case REV_ID_MAJOR_AR9341: + ath79_soc = ATH79_SOC_AR9341; + chip = "9341"; + rev = id & AR934X_REV_ID_REVISION_MASK; + break; + + case REV_ID_MAJOR_AR9342: + ath79_soc = ATH79_SOC_AR9342; + chip = "9342"; + rev = id & AR934X_REV_ID_REVISION_MASK; + break; + + case REV_ID_MAJOR_AR9344: + ath79_soc = ATH79_SOC_AR9344; + chip = "9344"; + rev = id & AR934X_REV_ID_REVISION_MASK; + break; + default: panic("ath79: unknown SoC, id:0x%08x", id); } |