diff options
| author | Len Brown <len.brown@intel.com> | 2009-01-09 03:39:43 -0500 |
|---|---|---|
| committer | Len Brown <len.brown@intel.com> | 2009-01-09 03:39:43 -0500 |
| commit | b2576e1d4408e134e2188c967b1f28af39cd79d4 (patch) | |
| tree | 004f3c82faab760f304ce031d6d2f572e7746a50 /arch/arm/plat-s3c24xx/include/plat/pll.h | |
| parent | 3cc8a5f4ba91f67bbdb81a43a99281a26aab8d77 (diff) | |
| parent | 2150edc6c5cf00f7adb54538b9ea2a3e9cedca3f (diff) | |
Merge branch 'linus' into release
Diffstat (limited to 'arch/arm/plat-s3c24xx/include/plat/pll.h')
| -rw-r--r-- | arch/arm/plat-s3c24xx/include/plat/pll.h | 37 |
1 files changed, 37 insertions, 0 deletions
diff --git a/arch/arm/plat-s3c24xx/include/plat/pll.h b/arch/arm/plat-s3c24xx/include/plat/pll.h new file mode 100644 index 000000000000..7ea8bffa7a9c --- /dev/null +++ b/arch/arm/plat-s3c24xx/include/plat/pll.h @@ -0,0 +1,37 @@ +/* linux/arch/arm/plat-s3c24xx/include/plat/pll.h + * + * Copyright 2008 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * http://armlinux.simtec.co.uk/ + * + * S3C24xx - common pll registers and code + */ + +#define S3C24XX_PLLCON_MDIVSHIFT 12 +#define S3C24XX_PLLCON_PDIVSHIFT 4 +#define S3C24XX_PLLCON_SDIVSHIFT 0 +#define S3C24XX_PLLCON_MDIVMASK ((1<<(1+(19-12)))-1) +#define S3C24XX_PLLCON_PDIVMASK ((1<<5)-1) +#define S3C24XX_PLLCON_SDIVMASK 3 + +#include <asm/div64.h> + +static inline unsigned int +s3c24xx_get_pll(unsigned int pllval, unsigned int baseclk) +{ + unsigned int mdiv, pdiv, sdiv; + uint64_t fvco; + + mdiv = pllval >> S3C24XX_PLLCON_MDIVSHIFT; + pdiv = pllval >> S3C24XX_PLLCON_PDIVSHIFT; + sdiv = pllval >> S3C24XX_PLLCON_SDIVSHIFT; + + mdiv &= S3C24XX_PLLCON_MDIVMASK; + pdiv &= S3C24XX_PLLCON_PDIVMASK; + sdiv &= S3C24XX_PLLCON_SDIVMASK; + + fvco = (uint64_t)baseclk * (mdiv + 8); + do_div(fvco, (pdiv + 2) << sdiv); + + return (unsigned int)fvco; +} |