diff options
| author | Catalin Marinas <catalin.marinas@arm.com> | 2008-04-18 22:43:08 +0100 |
|---|---|---|
| committer | Catalin Marinas <catalin.marinas@arm.com> | 2008-04-18 22:43:08 +0100 |
| commit | b7b0ba942f7b18de678cd081902aad8a0b6581c6 (patch) | |
| tree | 65e36cdf831906876bc558ab6d40db58d9ba5e92 /arch/arm/mm | |
| parent | cb170a45d69b573a08247acfbbff3b9d6e6e2f8f (diff) | |
RealView: Move the SCU initialisation out of __v6_setup
This patch moves the SCU initialisation from __v6_setup to the
smp_prepare_cpus() function as it relies on platform-specific
settings. Changes to get_core_count() are mainly for allowing cleaner
code with the upcoming PB11MPCore patches.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Diffstat (limited to 'arch/arm/mm')
| -rw-r--r-- | arch/arm/mm/proc-v6.S | 14 |
1 files changed, 0 insertions, 14 deletions
diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S index 2162a692d99a..bf760ea2f789 100644 --- a/arch/arm/mm/proc-v6.S +++ b/arch/arm/mm/proc-v6.S @@ -17,10 +17,6 @@ #include <asm/pgtable-hwdef.h> #include <asm/pgtable.h> -#ifdef CONFIG_SMP -#include <asm/hardware/arm_scu.h> -#endif - #include "proc-macros.S" #define D_CACHE_LINE_SIZE 32 @@ -187,20 +183,10 @@ cpu_v6_name: */ __v6_setup: #ifdef CONFIG_SMP - /* Set up the SCU on core 0 only */ - mrc p15, 0, r0, c0, c0, 5 @ CPU core number - ands r0, r0, #15 - ldreq r0, =SCU_BASE - ldreq r5, [r0, #SCU_CTRL] - orreq r5, r5, #1 - streq r5, [r0, #SCU_CTRL] - -#ifndef CONFIG_CPU_DCACHE_DISABLE mrc p15, 0, r0, c1, c0, 1 @ Enable SMP/nAMP mode orr r0, r0, #0x20 mcr p15, 0, r0, c1, c0, 1 #endif -#endif mov r0, #0 mcr p15, 0, r0, c7, c14, 0 @ clean+invalidate D cache |