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authorBenoit Cousson <b-cousson@ti.com>2010-12-21 21:08:34 -0700
committerPaul Walmsley <paul@pwsan.com>2010-12-21 21:08:34 -0700
commitb399bca897802db3f342b6f3032a19ab8f2af99b (patch)
tree88bff6a9e2ed7e60cc2f5c0a85c74434d711749d /arch/arm/mach-omap2/omap_hwmod_44xx_data.c
parent8f25bdc55d619bdd469a90b82743248680422507 (diff)
OMAP4: hwmod & clock data: Fix GPIO opt_clks and ocp_if iclk
Fix opt clocks name in clock framework and hwmod. Add the missing iclk in the ocp_if structure. Add the HWMOD_CONTROL_OPT_CLKS_IN_RESET flag to ensure the the GPIO optional clock is enable during reset. Signed-off-by: Benoit Cousson <b-cousson@ti.com> Tested-by: Charulatha V <charu@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Rajendra Nayak <rnayak@ti.com>
Diffstat (limited to 'arch/arm/mach-omap2/omap_hwmod_44xx_data.c')
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_44xx_data.c23
1 files changed, 17 insertions, 6 deletions
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index ad8015857f20..efc614de7f69 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -710,6 +710,7 @@ static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = {
static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = {
.master = &omap44xx_l4_wkup_hwmod,
.slave = &omap44xx_gpio1_hwmod,
+ .clk = "l4_wkup_clk_mux_ck",
.addr = omap44xx_gpio1_addrs,
.addr_cnt = ARRAY_SIZE(omap44xx_gpio1_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA,
@@ -721,7 +722,7 @@ static struct omap_hwmod_ocp_if *omap44xx_gpio1_slaves[] = {
};
static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
- { .role = "dbclk", .clk = "sys_32k_ck" },
+ { .role = "dbclk", .clk = "gpio1_dbclk" },
};
static struct omap_hwmod omap44xx_gpio1_hwmod = {
@@ -761,6 +762,7 @@ static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = {
static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = {
.master = &omap44xx_l4_per_hwmod,
.slave = &omap44xx_gpio2_hwmod,
+ .clk = "l4_div_ck",
.addr = omap44xx_gpio2_addrs,
.addr_cnt = ARRAY_SIZE(omap44xx_gpio2_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA,
@@ -772,12 +774,13 @@ static struct omap_hwmod_ocp_if *omap44xx_gpio2_slaves[] = {
};
static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
- { .role = "dbclk", .clk = "sys_32k_ck" },
+ { .role = "dbclk", .clk = "gpio2_dbclk" },
};
static struct omap_hwmod omap44xx_gpio2_hwmod = {
.name = "gpio2",
.class = &omap44xx_gpio_hwmod_class,
+ .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
.mpu_irqs = omap44xx_gpio2_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio2_irqs),
.main_clk = "gpio2_ick",
@@ -812,6 +815,7 @@ static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = {
static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = {
.master = &omap44xx_l4_per_hwmod,
.slave = &omap44xx_gpio3_hwmod,
+ .clk = "l4_div_ck",
.addr = omap44xx_gpio3_addrs,
.addr_cnt = ARRAY_SIZE(omap44xx_gpio3_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA,
@@ -823,12 +827,13 @@ static struct omap_hwmod_ocp_if *omap44xx_gpio3_slaves[] = {
};
static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
- { .role = "dbclk", .clk = "sys_32k_ck" },
+ { .role = "dbclk", .clk = "gpio3_dbclk" },
};
static struct omap_hwmod omap44xx_gpio3_hwmod = {
.name = "gpio3",
.class = &omap44xx_gpio_hwmod_class,
+ .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
.mpu_irqs = omap44xx_gpio3_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio3_irqs),
.main_clk = "gpio3_ick",
@@ -863,6 +868,7 @@ static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = {
static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = {
.master = &omap44xx_l4_per_hwmod,
.slave = &omap44xx_gpio4_hwmod,
+ .clk = "l4_div_ck",
.addr = omap44xx_gpio4_addrs,
.addr_cnt = ARRAY_SIZE(omap44xx_gpio4_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA,
@@ -874,12 +880,13 @@ static struct omap_hwmod_ocp_if *omap44xx_gpio4_slaves[] = {
};
static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
- { .role = "dbclk", .clk = "sys_32k_ck" },
+ { .role = "dbclk", .clk = "gpio4_dbclk" },
};
static struct omap_hwmod omap44xx_gpio4_hwmod = {
.name = "gpio4",
.class = &omap44xx_gpio_hwmod_class,
+ .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
.mpu_irqs = omap44xx_gpio4_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio4_irqs),
.main_clk = "gpio4_ick",
@@ -914,6 +921,7 @@ static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = {
static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = {
.master = &omap44xx_l4_per_hwmod,
.slave = &omap44xx_gpio5_hwmod,
+ .clk = "l4_div_ck",
.addr = omap44xx_gpio5_addrs,
.addr_cnt = ARRAY_SIZE(omap44xx_gpio5_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA,
@@ -925,12 +933,13 @@ static struct omap_hwmod_ocp_if *omap44xx_gpio5_slaves[] = {
};
static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
- { .role = "dbclk", .clk = "sys_32k_ck" },
+ { .role = "dbclk", .clk = "gpio5_dbclk" },
};
static struct omap_hwmod omap44xx_gpio5_hwmod = {
.name = "gpio5",
.class = &omap44xx_gpio_hwmod_class,
+ .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
.mpu_irqs = omap44xx_gpio5_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio5_irqs),
.main_clk = "gpio5_ick",
@@ -965,6 +974,7 @@ static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = {
static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = {
.master = &omap44xx_l4_per_hwmod,
.slave = &omap44xx_gpio6_hwmod,
+ .clk = "l4_div_ck",
.addr = omap44xx_gpio6_addrs,
.addr_cnt = ARRAY_SIZE(omap44xx_gpio6_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA,
@@ -976,12 +986,13 @@ static struct omap_hwmod_ocp_if *omap44xx_gpio6_slaves[] = {
};
static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
- { .role = "dbclk", .clk = "sys_32k_ck" },
+ { .role = "dbclk", .clk = "gpio6_dbclk" },
};
static struct omap_hwmod omap44xx_gpio6_hwmod = {
.name = "gpio6",
.class = &omap44xx_gpio_hwmod_class,
+ .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
.mpu_irqs = omap44xx_gpio6_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio6_irqs),
.main_clk = "gpio6_ick",