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authorYong Shen <yong.shen@linaro.org>2011-01-04 14:22:55 +0800
committerSascha Hauer <s.hauer@pengutronix.de>2011-01-04 12:00:23 +0100
commit644b1d586d6670262501057ae99d893fadb012de (patch)
tree429605722f136875036e708c56dde37386bda258 /arch/arm/mach-mx5/crm_regs.h
parent96de6d447f40612acb93f81a561a834177cca685 (diff)
ARM i.MX53: Some bug fix about MX53 MSL code
1. pll_base address should return right value 2. uart parent clk is from pll3 Signed-off-by: Yong Shen <yong.shen@linaro.org> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/arm/mach-mx5/crm_regs.h')
-rw-r--r--arch/arm/mach-mx5/crm_regs.h4
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/arm/mach-mx5/crm_regs.h b/arch/arm/mach-mx5/crm_regs.h
index 51ff9bb02379..b462c22f53d8 100644
--- a/arch/arm/mach-mx5/crm_regs.h
+++ b/arch/arm/mach-mx5/crm_regs.h
@@ -19,6 +19,10 @@
#define MX51_GPC_BASE MX51_IO_ADDRESS(MX51_GPC_BASE_ADDR)
/*MX53*/
+#define MX53_CCM_BASE MX53_IO_ADDRESS(MX53_CCM_BASE_ADDR)
+#define MX53_DPLL1_BASE MX53_IO_ADDRESS(MX53_PLL1_BASE_ADDR)
+#define MX53_DPLL2_BASE MX53_IO_ADDRESS(MX53_PLL2_BASE_ADDR)
+#define MX53_DPLL3_BASE MX53_IO_ADDRESS(MX53_PLL3_BASE_ADDR)
#define MX53_DPLL4_BASE MX53_IO_ADDRESS(MX53_PLL3_BASE_ADDR)
/* PLL Register Offsets */