diff options
| author | Arnd Bergmann <arnd@arndb.de> | 2012-07-17 23:25:58 +0200 |
|---|---|---|
| committer | Arnd Bergmann <arnd@arndb.de> | 2012-07-17 23:25:58 +0200 |
| commit | 77e77e1b61b422698a17da9eaafe6ce89dc242e2 (patch) | |
| tree | 398d0e7c2064a9d81c85cc699aa3a703a33451fa /arch/arm/mach-exynos/include/mach/regs-usb-phy.h | |
| parent | ff6091436239f618205bfcc86fb5bda4e28f47a1 (diff) | |
| parent | 2aa1ecf731fc4211a6b453167dff44c778789743 (diff) | |
Merge branch 'next/devel-samsung' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/soc
From Kukjin Kim <kgene.kim@samsung.com>:
This is general development for Samsung stuff for v3.6
* 'next/devel-samsung' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
ARM: SAMSUNG: Introduce Kconfig variable for Samsung custom clk API
ARM: EXYNOS: Add missing static storage class specifier in pmu.c file
ARM: EXYNOS: Make combiner_init function static
ARM: EXYNOS: Update HSOTG PHY clock setting for EXYNOS4X12
ARM: EXYNOS: Clear SYS_WDTRESET bit to use watchdog reset
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/arm/mach-exynos/include/mach/regs-usb-phy.h')
| -rw-r--r-- | arch/arm/mach-exynos/include/mach/regs-usb-phy.h | 20 |
1 files changed, 15 insertions, 5 deletions
diff --git a/arch/arm/mach-exynos/include/mach/regs-usb-phy.h b/arch/arm/mach-exynos/include/mach/regs-usb-phy.h index c337cf3a71bf..07277735252e 100644 --- a/arch/arm/mach-exynos/include/mach/regs-usb-phy.h +++ b/arch/arm/mach-exynos/include/mach/regs-usb-phy.h @@ -35,11 +35,21 @@ #define PHY1_COMMON_ON_N (1 << 7) #define PHY0_COMMON_ON_N (1 << 4) #define PHY0_ID_PULLUP (1 << 2) -#define CLKSEL_MASK (0x3 << 0) -#define CLKSEL_SHIFT (0) -#define CLKSEL_48M (0x0 << 0) -#define CLKSEL_12M (0x2 << 0) -#define CLKSEL_24M (0x3 << 0) + +#define EXYNOS4_CLKSEL_SHIFT (0) + +#define EXYNOS4210_CLKSEL_MASK (0x3 << 0) +#define EXYNOS4210_CLKSEL_48M (0x0 << 0) +#define EXYNOS4210_CLKSEL_12M (0x2 << 0) +#define EXYNOS4210_CLKSEL_24M (0x3 << 0) + +#define EXYNOS4X12_CLKSEL_MASK (0x7 << 0) +#define EXYNOS4X12_CLKSEL_9600K (0x0 << 0) +#define EXYNOS4X12_CLKSEL_10M (0x1 << 0) +#define EXYNOS4X12_CLKSEL_12M (0x2 << 0) +#define EXYNOS4X12_CLKSEL_19200K (0x3 << 0) +#define EXYNOS4X12_CLKSEL_20M (0x4 << 0) +#define EXYNOS4X12_CLKSEL_24M (0x5 << 0) #define EXYNOS4_RSTCON EXYNOS4_HSOTG_PHYREG(0x08) #define HOST_LINK_PORT_SWRST_MASK (0xf << 6) |