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authorSekhar Nori <nsekhar@ti.com>2010-07-20 16:46:51 +0530
committerKevin Hilman <khilman@deeprootsystems.com>2010-09-24 07:40:25 -0700
commitb987c4b2c9c9db2393f4c089e63d1734301214e5 (patch)
tree446b9ae602d8669e9e03107b976c9a88040b84ca /arch/arm/mach-davinci/include/mach/da8xx.h
parent30a2c5d2f0134df6175af26ce554aacaee304280 (diff)
davinci: am18x/da850/omap-l138: keep async clock constant with cpufreq
Keep PLL0 SYSCLK3 at a constant rate of 100MHz. This enables the AEMIF timing to remain valid even as the PLL0 output is changed by cpufreq driver to save power. Signed-off-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Diffstat (limited to 'arch/arm/mach-davinci/include/mach/da8xx.h')
-rw-r--r--arch/arm/mach-davinci/include/mach/da8xx.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mach-davinci/include/mach/da8xx.h b/arch/arm/mach-davinci/include/mach/da8xx.h
index 3c07059f526e..2c3f41897c17 100644
--- a/arch/arm/mach-davinci/include/mach/da8xx.h
+++ b/arch/arm/mach-davinci/include/mach/da8xx.h
@@ -78,7 +78,7 @@ int da8xx_register_lcdc(struct da8xx_lcdc_platform_data *pdata);
int da8xx_register_mmcsd0(struct davinci_mmc_config *config);
void __init da8xx_register_mcasp(int id, struct snd_platform_data *pdata);
int da8xx_register_rtc(void);
-int da850_register_cpufreq(void);
+int da850_register_cpufreq(char *async_clk);
int da8xx_register_cpuidle(void);
void __iomem * __init da8xx_get_mem_ctlr(void);
int da850_register_pm(struct platform_device *pdev);