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authorLinus Torvalds <torvalds@linux-foundation.org>2011-08-29 16:34:07 -0700
committerLinus Torvalds <torvalds@linux-foundation.org>2011-08-29 16:34:07 -0700
commit90e93648c41bd29a72f6ec55ce27a23c209eab8c (patch)
tree705afc522c361f681567187018d80cf028fcb334 /arch/arm/include/asm/pmu.h
parent3ae627b5a6c8f6bf992eee6a3399a1854641a476 (diff)
parent25904157168ddc8841748a729914f00e53d7e049 (diff)
Merge branch 'fixes' of master.kernel.org:/home/rmk/linux-2.6-arm
* 'fixes' of master.kernel.org:/home/rmk/linux-2.6-arm: ARM: pm: avoid writing the auxillary control register for ARMv7 ARM: pm: some ARMv7 requires a dsb in resume to ensure correctness ARM: pm: arm920/926: fix number of registers saved ARM: pm: CPU specific code should not overwrite r1 (v:p offset) ARM: 7066/1: proc-v7: disable SCTLR.TE when disabling MMU ARM: 7065/1: kexec: ensure new kernel is entered in ARM state ARM: 7003/1: vexpress: Add clock definition for the SP805. ARM: 7051/1: cpuimx* boards: fix mach-types errors ARM: 7019/1: Footbridge: select CLKEVT_I8253 for ARCH_NETWINDER ARM: 7015/1: ARM errata: Possible cache data corruption with hit-under-miss enabled ARM: 7014/1: cache-l2x0: Fix L2 Cache size calculation. ARM: 6967/1: ep93xx: ts72xx: fix board model detection ARM: 6965/1: ep93xx: add model detection for ts-7300 and ts-7400 boards ARM: cache: detect VIPT aliasing I-cache on ARMv6 ARM: twd: register clockevents device before enabling PPI ARM: realview: ensure visibility of writes during reset ARM: perf: make name of arm_pmu_type consistent ARM: perf: fix prototype of release_pmu ARM: fix perf build with uclibc toolchains
Diffstat (limited to 'arch/arm/include/asm/pmu.h')
-rw-r--r--arch/arm/include/asm/pmu.h10
1 files changed, 5 insertions, 5 deletions
diff --git a/arch/arm/include/asm/pmu.h b/arch/arm/include/asm/pmu.h
index 67c70a31a1be..b7e82c4aced6 100644
--- a/arch/arm/include/asm/pmu.h
+++ b/arch/arm/include/asm/pmu.h
@@ -41,7 +41,7 @@ struct arm_pmu_platdata {
* encoded error on failure.
*/
extern struct platform_device *
-reserve_pmu(enum arm_pmu_type device);
+reserve_pmu(enum arm_pmu_type type);
/**
* release_pmu() - Relinquish control of the performance counters
@@ -62,26 +62,26 @@ release_pmu(enum arm_pmu_type type);
* the actual hardware initialisation.
*/
extern int
-init_pmu(enum arm_pmu_type device);
+init_pmu(enum arm_pmu_type type);
#else /* CONFIG_CPU_HAS_PMU */
#include <linux/err.h>
static inline struct platform_device *
-reserve_pmu(enum arm_pmu_type device)
+reserve_pmu(enum arm_pmu_type type)
{
return ERR_PTR(-ENODEV);
}
static inline int
-release_pmu(struct platform_device *pdev)
+release_pmu(enum arm_pmu_type type)
{
return -ENODEV;
}
static inline int
-init_pmu(enum arm_pmu_type device)
+init_pmu(enum arm_pmu_type type)
{
return -ENODEV;
}