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authorLinus Torvalds <torvalds@linux-foundation.org>2010-05-19 11:37:22 -0700
committerLinus Torvalds <torvalds@linux-foundation.org>2010-05-19 11:37:22 -0700
commit1d3c6ff44ad4b5f113602e153026a338f0f9b3ff (patch)
tree1e1f2932634fc6d0e4acfe68496c1c727b83a13e /arch/arm/include/asm/perf_event.h
parent7c7cbaf5b82c418cd3b1dcf718f71d0e6057e639 (diff)
parent717e7c2672e37253a4d3aa70e4716b5b0a658761 (diff)
Merge branch 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm
* 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm: (224 commits) ARM: remove 'select GENERIC_TIME' ARM: 6136/1: ARCH_REQUIRE_GPIOLIB selects GENERIC_GPIO ARM: 6074/1: oprofile: convert from sysdev to platform device ARM: 6073/1: oprofile: remove old files and update KConfig ARM: 6072/1: oprofile: use perf-events framework as backend ARM: 6071/1: perf-events: allow modules to query the number of hardware counters ARM: 6070/1: perf-events: add support for xscale PMUs ARM: 6069/1: perf-events: use numeric ID to identify PMU ARM: 6064/1: pmu: register IRQs at runtime ARM: Optionally allow ARMv6 to use 'normal, bufferable' memory for DMA ARM: 6134/1: Handle instruction cache maintenance fault properly ARM: nwfpe: allow debugging output to be configured at runtime ARM: rename mach_cpu_disable() to platform_cpu_disable() ARM: 6132/1: PL330: Add common core driver ARM: 6094/1: Extend cache-l2x0 to support the 16-way PL310 ARM: Move memory mapping into mmu.c ARM: Ensure meminfo is sorted prior to sanity_check_meminfo ARM: Remove useless linux/bootmem.h includes ARM: convert /proc/cpu/aligment to seq_file arm: use asm-generic/scatterlist.h ...
Diffstat (limited to 'arch/arm/include/asm/perf_event.h')
-rw-r--r--arch/arm/include/asm/perf_event.h17
1 files changed, 17 insertions, 0 deletions
diff --git a/arch/arm/include/asm/perf_event.h b/arch/arm/include/asm/perf_event.h
index 49e3049aba32..48837e6d8887 100644
--- a/arch/arm/include/asm/perf_event.h
+++ b/arch/arm/include/asm/perf_event.h
@@ -28,4 +28,21 @@ set_perf_event_pending(void)
* same indexes here for consistency. */
#define PERF_EVENT_INDEX_OFFSET 1
+/* ARM perf PMU IDs for use by internal perf clients. */
+enum arm_perf_pmu_ids {
+ ARM_PERF_PMU_ID_XSCALE1 = 0,
+ ARM_PERF_PMU_ID_XSCALE2,
+ ARM_PERF_PMU_ID_V6,
+ ARM_PERF_PMU_ID_V6MP,
+ ARM_PERF_PMU_ID_CA8,
+ ARM_PERF_PMU_ID_CA9,
+ ARM_NUM_PMU_IDS,
+};
+
+extern enum arm_perf_pmu_ids
+armpmu_get_pmu_id(void);
+
+extern int
+armpmu_get_max_events(void);
+
#endif /* __ARM_PERF_EVENT_H__ */