diff options
| author | Matthias Brugger <matthias.bgg@gmail.com> | 2015-01-14 09:45:53 +0100 |
|---|---|---|
| committer | Matthias Brugger <matthias.bgg@gmail.com> | 2015-01-20 18:09:39 +0100 |
| commit | b8be56634b247e5dc892d8ec6d785e77a5f23845 (patch) | |
| tree | d07419f72f55790cccce0257e60bbe5d188df964 /arch/arm/boot/dts/mt6592.dtsi | |
| parent | 3aa2e2811ab58e0299bb9a6457a15b405be86ff0 (diff) | |
ARM: mediatek: dts: Add uart to mt6592
This patch adds the uart ports and the uart clock to Mediateks
mt6592 SoC.
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Diffstat (limited to 'arch/arm/boot/dts/mt6592.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/mt6592.dtsi | 38 |
1 files changed, 38 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/mt6592.dtsi b/arch/arm/boot/dts/mt6592.dtsi index 67c817418392..c69201ffff72 100644 --- a/arch/arm/boot/dts/mt6592.dtsi +++ b/arch/arm/boot/dts/mt6592.dtsi @@ -78,6 +78,12 @@ #clock-cells = <0>; }; + uart_clk: dummy26m { + compatible = "fixed-clock"; + clock-frequency = <26000000>; + #clock-cells = <0>; + }; + timer: timer@10008000 { compatible = "mediatek,mt6577-timer"; reg = <0x10008000 0x80>; @@ -102,4 +108,36 @@ reg = <0x10211000 0x1000>, <0x10212000 0x1000>; }; + + uart0: serial@11002000 { + compatible = "mediatek,mt6577-uart"; + reg = <0x11002000 0x400>; + interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>; + clocks = <&uart_clk>; + status = "disabled"; + }; + + uart1: serial@11003000 { + compatible = "mediatek,mt6577-uart"; + reg = <0x11003000 0x400>; + interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>; + clocks = <&uart_clk>; + status = "disabled"; + }; + + uart2: serial@11004000 { + compatible = "mediatek,mt6577-uart"; + reg = <0x11004000 0x400>; + interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>; + clocks = <&uart_clk>; + status = "disabled"; + }; + + uart3: serial@11005000 { + compatible = "mediatek,mt6577-uart"; + reg = <0x11005000 0x400>; + interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>; + clocks = <&uart_clk>; + status = "disabled"; + }; }; |