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authorChristopher Spinrath <christopher.spinrath@rwth-aachen.de>2016-11-11 16:59:39 +0100
committerShawn Guo <shawnguo@kernel.org>2016-11-14 15:33:13 +0800
commit425dd2773ed07d1ba21d4ada0f9a9abc85b75151 (patch)
tree9cf30b3a44da6bdfbcebdbea38598bd81cb43542 /arch/arm/boot/dts/imx6q-utilite-pro.dts
parentc4479f6f57a0821aae4f6ab6a91a23625d6b35a0 (diff)
ARM: dts: imx6q-utilite-pro: i2c1 is muxed
It turns out that the i2c1 adapter is connected to a multiplexer controlled by a gpio line. The first (default) mux option connects i2c1 to a bus connected to the already known peripherals. The other one connects the adapter to the ddc pins of the DVI port. Signed-off-by: Christopher Spinrath <christopher.spinrath@rwth-aachen.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat (limited to 'arch/arm/boot/dts/imx6q-utilite-pro.dts')
-rw-r--r--arch/arm/boot/dts/imx6q-utilite-pro.dts51
1 files changed, 40 insertions, 11 deletions
diff --git a/arch/arm/boot/dts/imx6q-utilite-pro.dts b/arch/arm/boot/dts/imx6q-utilite-pro.dts
index 61990630a748..246979a388a4 100644
--- a/arch/arm/boot/dts/imx6q-utilite-pro.dts
+++ b/arch/arm/boot/dts/imx6q-utilite-pro.dts
@@ -71,6 +71,40 @@
gpio-key,wakeup;
};
};
+
+ i2cmux {
+ compatible = "i2c-mux-gpio";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1mux>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mux-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
+ i2c-parent = <&i2c1>;
+
+ i2c@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ eeprom@50 {
+ compatible = "at24,24c02";
+ reg = <0x50>;
+ pagesize = <16>;
+ };
+
+ em3027: rtc@56 {
+ compatible = "emmicro,em3027";
+ reg = <0x56>;
+ };
+ };
+
+ i2c_dvi_ddc: i2c@1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
};
&hdmi {
@@ -82,17 +116,6 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
-
- eeprom@50 {
- compatible = "at24,24c02";
- reg = <0x50>;
- pagesize = <16>;
- };
-
- em3027: rtc@56 {
- compatible = "emmicro,em3027";
- reg = <0x56>;
- };
};
&i2c2 {
@@ -115,6 +138,12 @@
>;
};
+ pinctrl_i2c1mux: i2c1muxgrp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0
+ >;
+ };
+
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1