summaryrefslogtreecommitdiff
path: root/arch/arm/boot/dts/exynos5422-cpus.dtsi
diff options
context:
space:
mode:
authorThomas Abraham <thomas.ab@samsung.com>2015-12-15 18:33:17 +0100
committerKrzysztof Kozlowski <k.kozlowski@samsung.com>2016-01-28 19:30:26 +0900
commit66a4a1fb2398cc03637394a6ddfd077a5ee2acf4 (patch)
tree3a8f42d721c2eaab3269904f06cd423de37bf9da /arch/arm/boot/dts/exynos5422-cpus.dtsi
parent8b51c5e730fb66048f48437b17a024d2107347c3 (diff)
ARM: dts: Add CPU OPP properties for exynos542x/5800
For Exynos542x/5800 platforms, add CPU operating points for migrating from Exynos specific cpufreq driver to using generic cpufreq driver. Changes by Bartlomiej: - split Exynos5420 support from the original patch - merged Exynos5422 fixes from Ben Changes by Ben Gamari: - Port to operating-points-v2 Cc: Doug Anderson <dianders@chromium.org> Cc: Javier Martinez Canillas <javier@osg.samsung.com> Cc: Andreas Faerber <afaerber@suse.de> Signed-off-by: Thomas Abraham <thomas.ab@samsung.com> Signed-off-by: Ben Gamari <ben@smart-cactus.org> Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Diffstat (limited to 'arch/arm/boot/dts/exynos5422-cpus.dtsi')
-rw-r--r--arch/arm/boot/dts/exynos5422-cpus.dtsi10
1 files changed, 10 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/exynos5422-cpus.dtsi b/arch/arm/boot/dts/exynos5422-cpus.dtsi
index 33028ac76a33..9b46b9fbac4e 100644
--- a/arch/arm/boot/dts/exynos5422-cpus.dtsi
+++ b/arch/arm/boot/dts/exynos5422-cpus.dtsi
@@ -28,8 +28,10 @@
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x100>;
+ clocks = <&clock CLK_KFC_CLK>;
clock-frequency = <1000000000>;
cci-control-port = <&cci_control0>;
+ operating-points-v2 = <&cluster_a7_opp_table>;
};
cpu1: cpu@101 {
@@ -38,6 +40,7 @@
reg = <0x101>;
clock-frequency = <1000000000>;
cci-control-port = <&cci_control0>;
+ operating-points-v2 = <&cluster_a7_opp_table>;
};
cpu2: cpu@102 {
@@ -46,6 +49,7 @@
reg = <0x102>;
clock-frequency = <1000000000>;
cci-control-port = <&cci_control0>;
+ operating-points-v2 = <&cluster_a7_opp_table>;
};
cpu3: cpu@103 {
@@ -54,14 +58,17 @@
reg = <0x103>;
clock-frequency = <1000000000>;
cci-control-port = <&cci_control0>;
+ operating-points-v2 = <&cluster_a7_opp_table>;
};
cpu4: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a15";
+ clocks = <&clock CLK_ARM_CLK>;
reg = <0x0>;
clock-frequency = <1800000000>;
cci-control-port = <&cci_control1>;
+ operating-points-v2 = <&cluster_a15_opp_table>;
};
cpu5: cpu@1 {
@@ -70,6 +77,7 @@
reg = <0x1>;
clock-frequency = <1800000000>;
cci-control-port = <&cci_control1>;
+ operating-points-v2 = <&cluster_a15_opp_table>;
};
cpu6: cpu@2 {
@@ -78,6 +86,7 @@
reg = <0x2>;
clock-frequency = <1800000000>;
cci-control-port = <&cci_control1>;
+ operating-points-v2 = <&cluster_a15_opp_table>;
};
cpu7: cpu@3 {
@@ -86,6 +95,7 @@
reg = <0x3>;
clock-frequency = <1800000000>;
cci-control-port = <&cci_control1>;
+ operating-points-v2 = <&cluster_a15_opp_table>;
};
};
};