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authorMarek Szyprowski <m.szyprowski@samsung.com>2016-12-19 11:00:48 +0100
committerKrzysztof Kozlowski <krzk@kernel.org>2016-12-29 16:08:22 +0200
commit3590312f4773d3a3b3040c4a615bb79aada68a4c (patch)
tree19fb51ffd05336d64c50bbbcb96a01d6d8e417a0 /arch/arm/boot/dts/exynos5250.dtsi
parent287dad02e6590b00e4d8d5219993a2dca752b800 (diff)
ARM: dts: exynos: Enable DMA support for UART modules on Exynos5 SoCs
UART modules can use DMA for offloading data transfers and reducing interrupts, so enable this feature for Exynos5 boards. Tested on Google ChromeBook Snow (Exynos5250), Odroid XU (Exynos5410) and Odroid XU3 (Exynos5422) boards. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Tested-by: Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Diffstat (limited to 'arch/arm/boot/dts/exynos5250.dtsi')
-rw-r--r--arch/arm/boot/dts/exynos5250.dtsi8
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index b6d7444d8585..0e04460a815a 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -1043,21 +1043,29 @@
&serial_0 {
clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
clock-names = "uart", "clk_uart_baud0";
+ dmas = <&pdma0 13>, <&pdma0 14>;
+ dma-names = "rx", "tx";
};
&serial_1 {
clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
clock-names = "uart", "clk_uart_baud0";
+ dmas = <&pdma1 15>, <&pdma1 16>;
+ dma-names = "rx", "tx";
};
&serial_2 {
clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
clock-names = "uart", "clk_uart_baud0";
+ dmas = <&pdma0 15>, <&pdma0 16>;
+ dma-names = "rx", "tx";
};
&serial_3 {
clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
clock-names = "uart", "clk_uart_baud0";
+ dmas = <&pdma1 17>, <&pdma1 18>;
+ dma-names = "rx", "tx";
};
#include "exynos5250-pinctrl.dtsi"