diff options
| author | Masanari Iida <standby24x7@gmail.com> | 2015-07-06 23:41:57 +0900 |
|---|---|---|
| committer | Jonathan Corbet <corbet@lwn.net> | 2015-07-10 14:00:51 -0600 |
| commit | dc12f20ba06f89bc60d4dfadaf2b03404858e205 (patch) | |
| tree | 41186aaff0d6ff8ef5c761f81df69e4aea5597d0 /Documentation/powerpc/dscr.txt | |
| parent | 9ba6e988c7208e3cb1f71862cc578397ae938159 (diff) | |
Doc: powerpc: Fix typos in Documentation/powerpc
This patch fix some spelling typo found in Documentation/powerpc.
Signed-off-by: Masanari Iida <standby24x7@gmail.com>
Acked-by: Ian Munsie <imunsie@au1.ibm.com>
Signed-off-by: Jonathan Corbet <corbet@lwn.net>
Diffstat (limited to 'Documentation/powerpc/dscr.txt')
| -rw-r--r-- | Documentation/powerpc/dscr.txt | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/Documentation/powerpc/dscr.txt b/Documentation/powerpc/dscr.txt index 1ff4400c57b3..ece300c64f76 100644 --- a/Documentation/powerpc/dscr.txt +++ b/Documentation/powerpc/dscr.txt @@ -4,7 +4,7 @@ DSCR register in powerpc allows user to have some control of prefetch of data stream in the processor. Please refer to the ISA documents or related manual for more detailed information regarding how to use this DSCR to attain this -control of the pefetches . This document here provides an overview of kernel +control of the prefetches . This document here provides an overview of kernel support for DSCR, related kernel objects, it's functionalities and exported user interface. @@ -44,7 +44,7 @@ user interface. value into every CPU's DSCR register right away and updates the current thread's DSCR value as well. - Changing the CPU specif DSCR default value in the sysfs does exactly + Changing the CPU specific DSCR default value in the sysfs does exactly the same thing as above but unlike the global one above, it just changes stuff for that particular CPU instead for all the CPUs on the system. @@ -62,7 +62,7 @@ user interface. Accessing DSCR through user level SPR (0x03) from user space will first create a facility unavailable exception. Inside this exception handler - all mfspr isntruction based read attempts will get emulated and returned + all mfspr instruction based read attempts will get emulated and returned where as the first mtspr instruction based write attempts will enable the DSCR facility for the next time around (both for read and write) by setting DSCR facility in the FSCR register. |