diff options
| author | Mihai Sain <mihai.sain@microchip.com> | 2022-12-05 09:01:08 +0200 |
|---|---|---|
| committer | Claudiu Beznea <claudiu.beznea@microchip.com> | 2023-01-09 13:58:02 +0200 |
| commit | d4ac37916e42dc1a46e54bb7d49d5e39d7fa60d5 (patch) | |
| tree | b12cb1a5567e0f72b3c5562573ec6cec9bd0664f | |
| parent | 1b929c02afd37871d5afb9d498426f83432e71c2 (diff) | |
ARM: at91: add support in soc driver for new SAMA7G54 SiPs
Add detection of new SAMA7G54 System-In-Package (SIP) by the SoC driver:
SAMA7G54D1G, SAMA7G54D2G, SAMA7G54D4G.
Signed-off-by: Mihai Sain <mihai.sain@microchip.com>
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/20221205070108.42624-1-mihai.sain@microchip.com
| -rw-r--r-- | drivers/soc/atmel/soc.c | 9 | ||||
| -rw-r--r-- | drivers/soc/atmel/soc.h | 3 |
2 files changed, 12 insertions, 0 deletions
diff --git a/drivers/soc/atmel/soc.c b/drivers/soc/atmel/soc.c index dae8a2e0f745..cc9a3e107479 100644 --- a/drivers/soc/atmel/soc.c +++ b/drivers/soc/atmel/soc.c @@ -235,6 +235,15 @@ static const struct at91_soc socs[] __initconst = { AT91_SOC(SAMA7G5_CIDR_MATCH, AT91_CIDR_MATCH_MASK, AT91_CIDR_VERSION_MASK_SAMA7G5, SAMA7G54_EXID_MATCH, "sama7g54", "sama7g5"), + AT91_SOC(SAMA7G5_CIDR_MATCH, AT91_CIDR_MATCH_MASK, + AT91_CIDR_VERSION_MASK_SAMA7G5, SAMA7G54_D1G_EXID_MATCH, + "SAMA7G54 1Gb DDR3L SiP", "sama7g5"), + AT91_SOC(SAMA7G5_CIDR_MATCH, AT91_CIDR_MATCH_MASK, + AT91_CIDR_VERSION_MASK_SAMA7G5, SAMA7G54_D2G_EXID_MATCH, + "SAMA7G54 2Gb DDR3L SiP", "sama7g5"), + AT91_SOC(SAMA7G5_CIDR_MATCH, AT91_CIDR_MATCH_MASK, + AT91_CIDR_VERSION_MASK_SAMA7G5, SAMA7G54_D4G_EXID_MATCH, + "SAMA7G54 4Gb DDR3L SiP", "sama7g5"), #endif { /* sentinel */ }, }; diff --git a/drivers/soc/atmel/soc.h b/drivers/soc/atmel/soc.h index 2ecaa75b00f0..7a9f47ce85fb 100644 --- a/drivers/soc/atmel/soc.h +++ b/drivers/soc/atmel/soc.h @@ -70,6 +70,9 @@ at91_soc_init(const struct at91_soc *socs); #define SAMA7G52_EXID_MATCH 0x2 #define SAMA7G53_EXID_MATCH 0x1 #define SAMA7G54_EXID_MATCH 0x0 +#define SAMA7G54_D1G_EXID_MATCH 0x00000018 +#define SAMA7G54_D2G_EXID_MATCH 0x00000020 +#define SAMA7G54_D4G_EXID_MATCH 0x00000028 #define AT91SAM9XE128_CIDR_MATCH 0x329973a0 #define AT91SAM9XE256_CIDR_MATCH 0x329a93a0 |