From 1e65a3475f9314f713a46db782105a234bdf34cb Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Wed, 18 Nov 2015 15:19:57 -0800 Subject: MAINTAINERS: brcmstb: Include Broadcom internal mailing-list Include bcm-kernel-feedback-list for all brcmstb patch submission to be both consistent with how other Broadcom ARM-based SoCs are handled, and get internal Broadcom people to review these changes. Signed-off-by: Florian Fainelli --- MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/MAINTAINERS b/MAINTAINERS index e9caa4b28828..19b020df7d5a 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2356,6 +2356,7 @@ M: Brian Norris M: Gregory Fong M: Florian Fainelli L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) +L: bcm-kernel-feedback-list@broadcom.com T: git git://github.com/broadcom/stblinux.git S: Maintained F: arch/arm/mach-bcm/*brcmstb* -- cgit v1.2.3 From 9c2abe2f7159a6013004b6189a9867e880085e96 Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Wed, 18 Nov 2015 15:22:13 -0800 Subject: MAINTAINERS: gpio-brcmstb: Remove stray '>' There is a stray '>' at the end of the mailing-list specified for the Broadcom STB GPIO driver, remove that. Fixes: 3b0213d56eb7 ("gpio: Add GPIO support for Broadcom STB SoCs") Signed-off-by: Florian Fainelli --- MAINTAINERS | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index 19b020df7d5a..90975e56d05d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2430,7 +2430,7 @@ N: bcm88312 BROADCOM BRCMSTB GPIO DRIVER M: Gregory Fong -L: bcm-kernel-feedback-list@broadcom.com> +L: bcm-kernel-feedback-list@broadcom.com S: Supported F: drivers/gpio/gpio-brcmstb.c F: Documentation/devicetree/bindings/gpio/brcm,brcmstb-gpio.txt -- cgit v1.2.3 From 7f8f0b117ab8a22e7e5bb1faf8e8ea8a79005aec Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Thu, 3 Dec 2015 11:35:41 -0800 Subject: ARM: dts: Fix dm814x entries for pllss and prcm Otherwise drivers under pllss and prcm won't probe properly. Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dm814x.dtsi | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/dm814x.dtsi b/arch/arm/boot/dts/dm814x.dtsi index 7988b42e5764..5c8de1930c8b 100644 --- a/arch/arm/boot/dts/dm814x.dtsi +++ b/arch/arm/boot/dts/dm814x.dtsi @@ -215,7 +215,10 @@ prcm: prcm@180000 { compatible = "ti,dm814-prcm", "simple-bus"; - reg = <0x180000 0x4000>; + reg = <0x180000 0x2000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x180000 0x2000>; prcm_clocks: clocks { #address-cells = <1>; @@ -226,9 +229,13 @@ }; }; + /* See TRM PLL_SUBSYS_BASE and "PLLSS Registers" */ pllss: pllss@1c5000 { compatible = "ti,dm814-pllss", "simple-bus"; - reg = <0x1c5000 0x2000>; + reg = <0x1c5000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x1c5000 0x1000>; pllss_clocks: clocks { #address-cells = <1>; -- cgit v1.2.3 From 5fbeef5822781972d6fa054842cc7edca101f4bc Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Thu, 3 Dec 2015 12:02:31 -0800 Subject: clk: ti: Add few dm814x clock aliases The timer clock aliases are needed early on dm814x. Let's also add the aliases for the interconnects and MMC. Cc: Michael Turquette Cc: Stephen Boyd Acked-by: Tero Kristo Signed-off-by: Tony Lindgren --- drivers/clk/ti/clk-814x.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/clk/ti/clk-814x.c b/drivers/clk/ti/clk-814x.c index e172920798ea..9e85fcc74cc9 100644 --- a/drivers/clk/ti/clk-814x.c +++ b/drivers/clk/ti/clk-814x.c @@ -14,10 +14,14 @@ static struct ti_dt_clk dm814_clks[] = { DT_CLK(NULL, "devosc_ck", "devosc_ck"), DT_CLK(NULL, "mpu_ck", "mpu_ck"), DT_CLK(NULL, "sysclk4_ck", "sysclk4_ck"), + DT_CLK(NULL, "sysclk5_ck", "sysclk5_ck"), DT_CLK(NULL, "sysclk6_ck", "sysclk6_ck"), + DT_CLK(NULL, "sysclk8_ck", "sysclk8_ck"), DT_CLK(NULL, "sysclk10_ck", "sysclk10_ck"), DT_CLK(NULL, "sysclk18_ck", "sysclk18_ck"), DT_CLK(NULL, "timer_sys_ck", "devosc_ck"), + DT_CLK(NULL, "timer1_fck", "timer1_fck"), + DT_CLK(NULL, "timer2_fck", "timer2_fck"), DT_CLK(NULL, "cpsw_125mhz_gclk", "cpsw_125mhz_gclk"), DT_CLK(NULL, "cpsw_cpts_rft_clk", "cpsw_cpts_rft_clk"), { .node_name = NULL }, -- cgit v1.2.3 From 4e34df0cba14e95e941bf73721352fa4d9c2622f Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Thu, 3 Dec 2015 12:02:31 -0800 Subject: ARM: OMAP2+: Add DPPLS clock manager for dm814x On dm814x we have some clocks at DPLLS and some at PRCM. Let's add a new omap_prcm_init_data entry for the DPLLS so we can initalize timer clocks early. Cc: Paul Walmsley Cc: Tero Kristo Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/prm_common.c | 6 ++++++ include/linux/clk/ti.h | 1 + 2 files changed, 7 insertions(+) diff --git a/arch/arm/mach-omap2/prm_common.c b/arch/arm/mach-omap2/prm_common.c index 3fc2cbe52113..55acc76113b8 100644 --- a/arch/arm/mach-omap2/prm_common.c +++ b/arch/arm/mach-omap2/prm_common.c @@ -662,6 +662,11 @@ static struct omap_prcm_init_data am3_prm_data __initdata = { .index = TI_CLKM_PRM, .init = am33xx_prm_init, }; + +static struct omap_prcm_init_data dm814_pllss_data __initdata = { + .index = TI_CLKM_PLLSS, + .init = am33xx_prm_init, +}; #endif #ifdef CONFIG_ARCH_OMAP4 @@ -715,6 +720,7 @@ static const struct of_device_id const omap_prcm_dt_match_table[] __initconst = #endif #ifdef CONFIG_SOC_TI81XX { .compatible = "ti,dm814-prcm", .data = &am3_prm_data }, + { .compatible = "ti,dm814-pllss", .data = &dm814_pllss_data }, { .compatible = "ti,dm816-prcm", .data = &am3_prm_data }, #endif #ifdef CONFIG_ARCH_OMAP2 diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h index 223be696df27..57663c162e1c 100644 --- a/include/linux/clk/ti.h +++ b/include/linux/clk/ti.h @@ -195,6 +195,7 @@ enum { TI_CLKM_PRM, TI_CLKM_SCRM, TI_CLKM_CTRL, + TI_CLKM_PLLSS, CLK_MAX_MEMMAPS }; -- cgit v1.2.3 From 9079446dbca399f786f2e580944c011b3072b766 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Thu, 3 Dec 2015 12:02:31 -0800 Subject: ARM: dts: Fix some mux and divider clocks to get dm814x-evm booting Although we have hp t410 booting, I noticed that dm814x-evm does not boot after I got one. This is because we don't have the clocks yet configured properly. Let's start configuring proper clocks starting with the system timers and clocks that work with existing mux and divider clock drivers. Note that the oscillator speed register is different from am335x, dm814x has only one bit that shows the BTMODE[6] at CONTROL_STATUS[21]. Also note that this only gets the system timers working with the defined clocks. The PLL clocks are still missing and and the devices may or may not work depending on what the bootloader has enabled. Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dm814x-clocks.dtsi | 109 +++++++++++++++++++++++++---------- 1 file changed, 79 insertions(+), 30 deletions(-) diff --git a/arch/arm/boot/dts/dm814x-clocks.dtsi b/arch/arm/boot/dts/dm814x-clocks.dtsi index ef1e8e7a6cc6..26001585673a 100644 --- a/arch/arm/boot/dts/dm814x-clocks.dtsi +++ b/arch/arm/boot/dts/dm814x-clocks.dtsi @@ -4,25 +4,74 @@ * published by the Free Software Foundation. */ +&pllss_clocks { + timer1_fck: timer1_fck { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&sysclk18_ck &aud_clkin0_ck &aud_clkin1_ck + &aud_clkin2_ck &devosc_ck &auxosc_ck &tclkin_ck>; + ti,bit-shift = <3>; + reg = <0x2e0>; + }; + + timer2_fck: timer2_fck { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&sysclk18_ck &aud_clkin0_ck &aud_clkin1_ck + &aud_clkin2_ck &devosc_ck &auxosc_ck &tclkin_ck>; + ti,bit-shift = <6>; + reg = <0x2e0>; + }; + + sysclk18_ck: sysclk18_ck { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&rtcosc_ck>, <&rtcdivider_ck>; + ti,bit-shift = <0>; + reg = <0x02f0>; + }; +}; + &scm_clocks { + devosc_ck: devosc_ck { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&virt_20000000_ck>, <&virt_19200000_ck>; + ti,bit-shift = <21>; + reg = <0x0040>; + }; - tclkin_ck: tclkin_ck { + /* Optional auxosc, 20 - 30 MHz range, assume 27 MHz by default */ + auxosc_ck: auxosc_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <27000000>; + }; + + /* Optional 32768Hz crystal or clock on RTCOSC pins */ + rtcosc_ck: rtcosc_ck { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <32768>; }; - devosc_ck: devosc_ck { + /* Optional external clock on TCLKIN pin, set rate in baord dts file */ + tclkin_ck: tclkin_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; + }; + + virt_20000000_ck: virt_20000000_ck { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <20000000>; }; - /* Optional auxosc, 20 - 30 MHz range, assume 27 MHz by default */ - auxosc_ck: auxosc_ck { + virt_19200000_ck: virt_19200000_ck { #clock-cells = <0>; compatible = "fixed-clock"; - clock-frequency = <27000000>; + clock-frequency = <19200000>; }; mpu_ck: mpu_ck { @@ -49,12 +98,6 @@ clock-frequency = <48000000>; }; - sysclk18_ck: sysclk18_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - }; - cpsw_125mhz_gclk: cpsw_125mhz_gclk { #clock-cells = <0>; compatible = "fixed-clock"; @@ -69,7 +112,31 @@ }; -&pllss_clocks { +&prcm_clocks { + osc_src_ck: osc_src_ck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&devosc_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + mpu_clksrc_ck: mpu_clksrc_ck { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&devosc_ck>, <&rtcdivider_ck>; + ti,bit-shift = <0>; + reg = <0x0040>; + }; + + /* Fixed divider clock 0.0016384 * devosc */ + rtcdivider_ck: rtcdivider_ck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&devosc_ck>; + clock-mult = <128>; + clock-div = <78125>; + }; aud_clkin0_ck: aud_clkin0_ck { #clock-cells = <0>; @@ -88,22 +155,4 @@ compatible = "fixed-clock"; clock-frequency = <20000000>; }; - - timer1_mux_ck: timer1_mux_ck { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sysclk18_ck &aud_clkin0_ck &aud_clkin1_ck - &aud_clkin2_ck &devosc_ck &auxosc_ck &tclkin_ck>; - ti,bit-shift = <3>; - reg = <0x2e0>; - }; - - timer2_mux_ck: timer2_mux_ck { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sysclk18_ck &aud_clkin0_ck &aud_clkin1_ck - &aud_clkin2_ck &devosc_ck &auxosc_ck &tclkin_ck>; - ti,bit-shift = <6>; - reg = <0x2e0>; - }; }; -- cgit v1.2.3 From cb4db0381a9330640a036076c0d5457d39af38ab Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Thu, 3 Dec 2015 12:02:31 -0800 Subject: ARM: OMAP2+: Fix timer entries for dm814x There's a mux after the oscillator similar to am335x. I did not notice this on hp t410 as it boots even with no clocks configured. Cc: Paul Walmsley Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/omap_hwmod_81xx_data.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/mach-omap2/omap_hwmod_81xx_data.c b/arch/arm/mach-omap2/omap_hwmod_81xx_data.c index 6256052893ec..d5246b351d0b 100644 --- a/arch/arm/mach-omap2/omap_hwmod_81xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_81xx_data.c @@ -599,7 +599,7 @@ static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = { static struct omap_hwmod dm814x_timer1_hwmod = { .name = "timer1", .clkdm_name = "alwon_l3s_clkdm", - .main_clk = "timer_sys_ck", + .main_clk = "timer1_fck", .dev_attr = &capability_alwon_dev_attr, .class = &dm816x_timer_hwmod_class, .flags = HWMOD_NO_IDLEST, @@ -608,7 +608,7 @@ static struct omap_hwmod dm814x_timer1_hwmod = { static struct omap_hwmod_ocp_if dm814x_l4_ls__timer1 = { .master = &dm81xx_l4_ls_hwmod, .slave = &dm814x_timer1_hwmod, - .clk = "timer_sys_ck", + .clk = "timer1_fck", .user = OCP_USER_MPU, }; @@ -636,7 +636,7 @@ static struct omap_hwmod_ocp_if dm816x_l4_ls__timer1 = { static struct omap_hwmod dm814x_timer2_hwmod = { .name = "timer2", .clkdm_name = "alwon_l3s_clkdm", - .main_clk = "timer_sys_ck", + .main_clk = "timer2_fck", .dev_attr = &capability_alwon_dev_attr, .class = &dm816x_timer_hwmod_class, .flags = HWMOD_NO_IDLEST, @@ -645,7 +645,7 @@ static struct omap_hwmod dm814x_timer2_hwmod = { static struct omap_hwmod_ocp_if dm814x_l4_ls__timer2 = { .master = &dm81xx_l4_ls_hwmod, .slave = &dm814x_timer2_hwmod, - .clk = "timer_sys_ck", + .clk = "timer2_fck", .user = OCP_USER_MPU, }; -- cgit v1.2.3 From 3a91b0616a97c1cdfc5955082c5999663defd54e Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Thu, 3 Dec 2015 12:02:32 -0800 Subject: ARM: dts: Fix dm8148 control modules ranges The control module is at offset 0x14000 with size 0x20000, not 0x16000. This causes the pinctrl driver to not work. Let's also fix the comments related to the TRM "L4LS Instance Summary" table as that's what's causing the bad entries. Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dm814x.dtsi | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/dm814x.dtsi b/arch/arm/boot/dts/dm814x.dtsi index 5c8de1930c8b..68b156b52003 100644 --- a/arch/arm/boot/dts/dm814x.dtsi +++ b/arch/arm/boot/dts/dm814x.dtsi @@ -58,8 +58,10 @@ ti,hwmods = "l3_main"; /* - * See TRM "Table 1-317. L4LS Instance Summary", just deduct - * 0x1000 from the 1-317 addresses to get the device address + * See TRM "Table 1-317. L4LS Instance Summary" for hints. + * It shows the module target agent registers though, so the + * actual device is typically 0x1000 before the target agent + * except in cases where the module is larger than 0x1000. */ l4ls: l4ls@48000000 { compatible = "ti,dm814-l4ls", "simple-bus"; @@ -183,10 +185,10 @@ control: control@140000 { compatible = "ti,dm814-scm", "simple-bus"; - reg = <0x140000 0x16d000>; + reg = <0x140000 0x20000>; #address-cells = <1>; #size-cells = <1>; - ranges = <0 0x160000 0x16d000>; + ranges = <0 0x140000 0x20000>; scm_conf: scm_conf@0 { compatible = "syscon"; -- cgit v1.2.3 From 9621557fc31f5e42f026217d67db023ebfe903c9 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Thu, 3 Dec 2015 12:02:32 -0800 Subject: ARM: dts: Fix dm814x pinctrl address and mask Otherwise pinctrl won't work. Because of silicon errata for some dm814x versions, let's also keep bit 18 out of the function-mask and rely on the bootloader configuration for bit 18 as suggested by Matthijs van Duin . Devices with that need to use bit 18 can override the function-mask in the board specific dts file if really needed. Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dm814x.dtsi | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/dm814x.dtsi b/arch/arm/boot/dts/dm814x.dtsi index 68b156b52003..09a8d88bde23 100644 --- a/arch/arm/boot/dts/dm814x.dtsi +++ b/arch/arm/boot/dts/dm814x.dtsi @@ -205,13 +205,21 @@ }; }; + /* + * Note that silicon revision 2.1 and older + * require input enabled (bit 18 set) for all + * 3.3V I/Os to avoid cumulative hardware damage. + * For more info, see errata advisory 2.1.87. + * We leave bit 18 out of function-mask and rely + * on the bootloader for it. + */ pincntl: pinmux@800 { compatible = "pinctrl-single"; - reg = <0x800 0xc38>; + reg = <0x800 0x438>; #address-cells = <1>; #size-cells = <0>; pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0x300ff>; + pinctrl-single,function-mask = <0x307ff>; }; }; -- cgit v1.2.3 From 3022b29df67729c42acbd20f6c3e5ba8f8b60741 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Thu, 3 Dec 2015 12:02:32 -0800 Subject: ARM: OMAP2+: Enable GPIO for dm814x With the basic clocks now working we can enable GPIO. Cc: Paul Walmsley Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/omap_hwmod_81xx_data.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-omap2/omap_hwmod_81xx_data.c b/arch/arm/mach-omap2/omap_hwmod_81xx_data.c index d5246b351d0b..1b96cdfd1558 100644 --- a/arch/arm/mach-omap2/omap_hwmod_81xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_81xx_data.c @@ -1230,8 +1230,6 @@ static struct omap_hwmod_ocp_if dm81xx_tptc3__alwon_l3_fast = { /* * REVISIT: Test and enable the following once clocks work: - * dm81xx_l4_ls__gpio1 - * dm81xx_l4_ls__gpio2 * dm81xx_l4_ls__mailbox * dm81xx_alwon_l3_slow__gpmc * dm81xx_default_l3_slow__usbss @@ -1250,6 +1248,8 @@ static struct omap_hwmod_ocp_if *dm814x_hwmod_ocp_ifs[] __initdata = { &dm81xx_l4_ls__wd_timer1, &dm81xx_l4_ls__i2c1, &dm81xx_l4_ls__i2c2, + &dm81xx_l4_ls__gpio1, + &dm81xx_l4_ls__gpio2, &dm81xx_l4_ls__elm, &dm81xx_l4_ls__mcspi1, &dm81xx_alwon_l3_fast__tpcc, -- cgit v1.2.3 From d893656e61040f3ff7b5f72a986052a348f3c94e Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Thu, 3 Dec 2015 12:02:32 -0800 Subject: ARM: OMAP2+: Remove useless check for legacy booting for dm814x We have never had dm814x booting properly with mainline kernel using the legacy platform data based booting. Current minimal support is device tree only. Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/io.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c index 3eaeaca5da05..3c87e40650cf 100644 --- a/arch/arm/mach-omap2/io.c +++ b/arch/arm/mach-omap2/io.c @@ -612,8 +612,7 @@ void __init ti814x_init_early(void) ti814x_clockdomains_init(); dm814x_hwmod_init(); omap_hwmod_init_postsetup(); - if (of_have_populated_dt()) - omap_clk_soc_init = dm814x_dt_clk_init; + omap_clk_soc_init = dm814x_dt_clk_init; } void __init ti816x_init_early(void) -- cgit v1.2.3 From 1b50b0c1ceb5652e5ee985b52761a414ceecbe20 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Thu, 10 Dec 2015 14:19:20 +0100 Subject: ARM: davinci: only select WT cache if cache is enabled The DA830 chip only works if the dcache is in writethrough mode, but that produces a harmless Kconfig warning if the cache happens to be disabled: warning: (ARCH_DAVINCI_DA830) selects CPU_DCACHE_WRITETHROUGH which has unmet direct dependencies ((CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_FA526) && !CPU_DCACHE_DISABLE) This makes the select conditional so we don't have to worry about the warning in randconfig builds any more. Signed-off-by: Arnd Bergmann Signed-off-by: Sekhar Nori --- arch/arm/mach-davinci/Kconfig | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig index dd8f5312b2c0..bcaf1d025505 100644 --- a/arch/arm/mach-davinci/Kconfig +++ b/arch/arm/mach-davinci/Kconfig @@ -34,7 +34,8 @@ config ARCH_DAVINCI_DA830 bool "DA830/OMAP-L137/AM17x based system" depends on !ARCH_DAVINCI_DMx || AUTO_ZRELADDR select ARCH_DAVINCI_DA8XX - select CPU_DCACHE_WRITETHROUGH # needed on silicon revs 1.0, 1.1 + # needed on silicon revs 1.0, 1.1: + select CPU_DCACHE_WRITETHROUGH if !CPU_DCACHE_DISABLE select CP_INTC config ARCH_DAVINCI_DA850 -- cgit v1.2.3 From 5bcd927233d18fbfabed461b31b0118147648525 Mon Sep 17 00:00:00 2001 From: Geliang Tang Date: Thu, 26 Nov 2015 08:35:27 +0800 Subject: ARM: davinci: fix a problematic usage of WARN() WARN() takes a condition and a format string. The condition was omitted. So I added it. Signed-off-by: Geliang Tang Signed-off-by: Sekhar Nori --- arch/arm/mach-davinci/board-dm355-evm.c | 4 +--- arch/arm/mach-davinci/board-dm355-leopard.c | 4 +--- 2 files changed, 2 insertions(+), 6 deletions(-) diff --git a/arch/arm/mach-davinci/board-dm355-evm.c b/arch/arm/mach-davinci/board-dm355-evm.c index b46b4d25f93e..f80873e4215d 100644 --- a/arch/arm/mach-davinci/board-dm355-evm.c +++ b/arch/arm/mach-davinci/board-dm355-evm.c @@ -384,9 +384,7 @@ static __init void dm355_evm_init(void) dm355evm_dm9000_rsrc[2].start = gpio_to_irq(1); aemif = clk_get(&dm355evm_dm9000.dev, "aemif"); - if (IS_ERR(aemif)) - WARN("%s: unable to get AEMIF clock\n", __func__); - else + if (!WARN(IS_ERR(aemif), "unable to get AEMIF clock\n")) clk_prepare_enable(aemif); platform_add_devices(davinci_evm_devices, diff --git a/arch/arm/mach-davinci/board-dm355-leopard.c b/arch/arm/mach-davinci/board-dm355-leopard.c index 680a7a2d9102..284ff27c1b32 100644 --- a/arch/arm/mach-davinci/board-dm355-leopard.c +++ b/arch/arm/mach-davinci/board-dm355-leopard.c @@ -242,9 +242,7 @@ static __init void dm355_leopard_init(void) dm355leopard_dm9000_rsrc[2].start = gpio_to_irq(9); aemif = clk_get(&dm355leopard_dm9000.dev, "aemif"); - if (IS_ERR(aemif)) - WARN("%s: unable to get AEMIF clock\n", __func__); - else + if (!WARN(IS_ERR(aemif), "unable to get AEMIF clock\n")) clk_prepare_enable(aemif); platform_add_devices(davinci_leopard_devices, -- cgit v1.2.3 From 86d5e657d27851beb0e3e7bf48f13263acc5196a Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Tue, 22 Dec 2015 15:35:47 +0100 Subject: ARM: scoop: Be sure to clamp return value As we want gpio_chip .get() calls to be able to return negative error codes and propagate to drivers, we need to go over all drivers and make sure their return values are clamped to [0,1]. We do this by using the ret = !!(val) design pattern. Cc: arm@kernel.org Cc: Richard Purdie Signed-off-by: Linus Walleij Signed-off-by: Olof Johansson --- arch/arm/common/scoop.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/common/scoop.c b/arch/arm/common/scoop.c index 45f4c21e393c..e0df333202b8 100644 --- a/arch/arm/common/scoop.c +++ b/arch/arm/common/scoop.c @@ -84,7 +84,7 @@ static int scoop_gpio_get(struct gpio_chip *chip, unsigned offset) struct scoop_dev *sdev = container_of(chip, struct scoop_dev, gpio); /* XXX: I'm unsure, but it seems so */ - return ioread16(sdev->base + SCOOP_GPRR) & (1 << (offset + 1)); + return !!(ioread16(sdev->base + SCOOP_GPRR) & (1 << (offset + 1))); } static int scoop_gpio_direction_input(struct gpio_chip *chip, -- cgit v1.2.3 From 1f33b0131a15f4dc6b2fff9d3ef9d002070bda40 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Tue, 22 Dec 2015 15:36:12 +0100 Subject: ARM: sa1100/simpad: Be sure to clamp return value As we want gpio_chip .get() calls to be able to return negative error codes and propagate to drivers, we need to go over all drivers and make sure their return values are clamped to [0,1]. We do this by using the ret = !!(val) design pattern. Cc: arm@kernel.org Signed-off-by: Linus Walleij Signed-off-by: Olof Johansson --- arch/arm/mach-sa1100/simpad.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-sa1100/simpad.c b/arch/arm/mach-sa1100/simpad.c index 41e476e571d7..d8965c682d2f 100644 --- a/arch/arm/mach-sa1100/simpad.c +++ b/arch/arm/mach-sa1100/simpad.c @@ -98,8 +98,8 @@ static void cs3_gpio_set(struct gpio_chip *chip, unsigned offset, int value) static int cs3_gpio_get(struct gpio_chip *chip, unsigned offset) { if (offset > 15) - return simpad_get_cs3_ro() & (1 << (offset - 16)); - return simpad_get_cs3_shadow() & (1 << offset); + return !!(simpad_get_cs3_ro() & (1 << (offset - 16))); + return !!(simpad_get_cs3_shadow() & (1 << offset)); }; static int cs3_gpio_direction_input(struct gpio_chip *chip, unsigned offset) -- cgit v1.2.3 From dbb7e70a69288980c8a89fdb5ffb97e06b806b19 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Mon, 21 Dec 2015 10:06:52 -0800 Subject: ARM: OMAP2+: Fix randconfig build warning for dm814_pllss_data MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Fix warning for arch/arm/mach-omap2/prm_common.c:666:35: warning: ‘dm814_pllss_data’ defined but not used [-Wunused-variable]". This can happen if CONFIG_SOC_TI81XX is not selected. Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/prm_common.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/mach-omap2/prm_common.c b/arch/arm/mach-omap2/prm_common.c index 55acc76113b8..5b2f5138d938 100644 --- a/arch/arm/mach-omap2/prm_common.c +++ b/arch/arm/mach-omap2/prm_common.c @@ -662,7 +662,9 @@ static struct omap_prcm_init_data am3_prm_data __initdata = { .index = TI_CLKM_PRM, .init = am33xx_prm_init, }; +#endif +#ifdef CONFIG_SOC_TI81XX static struct omap_prcm_init_data dm814_pllss_data __initdata = { .index = TI_CLKM_PLLSS, .init = am33xx_prm_init, -- cgit v1.2.3