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2016-05-09Merge tag 'v4.6-next-soc' of https://github.com/mbgg/linux-mediatek into ↵Arnd Bergmann1-131/+413
next/drivers Merge "ARM: mediatek soc updates for v4.7" from Matthias Brugger: - re-organize pmic wrapper code for easier and cleaner addiont of new SoCs and pmic wrappers - add support for pmic wrapper mt6323 - add support for SoC mt2701 - enable gpt6 arch timer on mt7623 * tag 'v4.6-next-soc' of https://github.com/mbgg/linux-mediatek: ARM: mediatek: enable gpt6 on boot up to make arch timer work on mt7623 soc: mediatek: PMIC wrap: add MT2701/7623 support soc: mediatek: PMIC wrap: add mt6323 slave support soc: mediatek: PMIC wrap: add a slave specific struct soc: mediatek: PMIC wrap: remove pwrap_is_mt8135() and pwrap_is_mt8173() soc: mediatek: PMIC wrap: move wdt_src into the pmic_wrapper_type struct soc: mediatek: PMIC wrap: SPI_WRITE needs a different bitmask for MT2701/7623 soc: mediatek: PMIC wrap: WRAP_INT_EN needs a different bitmask for MT2701/7623 soc: mediatek: PMIC wrap: split SoC specific init into callback soc: mediatek: PMIC wrap: add wrapper callbacks for init_reg_clock soc: mediatek: PMIC wrap: don't duplicate the wrapper data
2016-05-09Merge tag 'tegra-for-4.7-genpd' of ↵Arnd Bergmann1-61/+424
git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/drivers Merge "soc/tegra: Add generic PM domain support" from Thierry Reding: Implements generic PM domain support on top of the existing Tegra power- gate API. Drivers are thus allowed to move away from the Tegra-specific API and towards using generic power domains directly. * tag 'tegra-for-4.7-genpd' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: soc/tegra: pmc: Add generic PM domain support dt-bindings: Add power domain info for NVIDIA PMC
2016-05-09Merge tag 'v4.7-rockchip-drivers-2' of ↵Arnd Bergmann1-3/+102
git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into next/drivers Merge "Rockchip driver updates for v4.7 - part2" from Heiko Stübner: Ability to save and restore the power-domain quality of service settings that get lost and reset on power-domain power cycles. * tag 'v4.7-rockchip-drivers-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: soc: rockchip: power-domain: support qos save and restore dt-bindings: modify document of Rockchip power domains
2016-04-29soc/tegra: pmc: Add generic PM domain supportJon Hunter1-61/+424
Adds generic PM domain support to the PMC driver where the PM domains are populated from device-tree and the PM domain consumer devices are bound to their relevant PM domains via device-tree as well. Update the tegra_powergate_sequence_power_up() API so that internally it calls the same tegra_powergate_xxx functions that are used by the Tegra generic PM domain code for consistency. To ensure that the Tegra power domains (a.k.a. powergates) cannot be controlled via both the legacy tegra_powergate_xxx functions as well as the generic PM domain framework, add a bit map for available powergates that can be controlled via the legacy powergate functions. Move the majority of the tegra_powergate_remove_clamping() function to a sub-function, so that this can be used by both the legacy and generic power domain code. This is based upon work by Thierry Reding <treding@nvidia.com> and Vince Hsu <vinceh@nvidia.com>. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-04-26Merge tag 'renesas-rcar-sysc2-for-v4.7' of ↵Arnd Bergmann9-1/+672
git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/drivers Merge "Second Round of Renesas ARM Based SoC R-Car SYSC Updates for v4.7" from Simon Horman: Introduce a DT-based driver for the R-Car System Controller, as found on Renesas R-Car H1, R-Car Gen2, and R-Car Gen3 SoCs. * tag 'renesas-rcar-sysc2-for-v4.7' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (30 commits) soc: renesas: rcar-sysc: Add support for R-Car H3 power areas soc: renesas: rcar-sysc: Add support for R-Car E2 power areas soc: renesas: rcar-sysc: Add support for R-Car M2-N power areas soc: renesas: rcar-sysc: Add support for R-Car M2-W power areas soc: renesas: rcar-sysc: Add support for R-Car H2 power areas soc: renesas: rcar-sysc: Add support for R-Car H1 power areas soc: renesas: rcar-sysc: Enable Clock Domain for I/O devices soc: renesas: rcar-sysc: Make rcar_sysc_power_is_off() static soc: renesas: rcar-sysc: Add DT support for SYSC PM domains soc: renesas: rcar-sysc: Improve rcar_sysc_power() debug info soc: renesas: Move pm-rcar to drivers/soc/renesas/rcar-sysc clk: renesas: cpg-mssr: Export cpg_mssr_{at,de}tach_dev() clk: renesas: mstp: Provide dummy attach/detach_dev callbacks clk: renesas: Provide Kconfig symbols for CPG/MSSR and CPG/MSTP support soc: renesas: Add r8a7795 SYSC PM Domain Binding Definitions soc: renesas: Add r8a7794 SYSC PM Domain Binding Definitions soc: renesas: Add r8a7793 SYSC PM Domain Binding Definitions soc: renesas: Add r8a7791 SYSC PM Domain Binding Definitions soc: renesas: Add r8a7790 SYSC PM Domain Binding Definitions soc: renesas: Add r8a7779 SYSC PM Domain Binding Definitions ...
2016-04-26soc: renesas: rcar-sysc: Add support for R-Car H3 power areasGeert Uytterhoeven4-0/+61
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2016-04-26soc: renesas: rcar-sysc: Add support for R-Car E2 power areasGeert Uytterhoeven4-1/+38
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2016-04-26soc: renesas: rcar-sysc: Add support for R-Car M2-N power areasGeert Uytterhoeven2-1/+6
R-Car M2-N is identical to R-Car M2-W w.r.t. power domains, so reuse the definitions from the latter. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2016-04-26soc: renesas: rcar-sysc: Add support for R-Car M2-W power areasGeert Uytterhoeven4-1/+38
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2016-04-26soc: renesas: rcar-sysc: Add support for R-Car H2 power areasGeert Uytterhoeven4-1/+53
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2016-04-26soc: renesas: rcar-sysc: Add support for R-Car H1 power areasGeert Uytterhoeven4-1/+39
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2016-04-26soc: renesas: rcar-sysc: Enable Clock Domain for I/O devicesGeert Uytterhoeven1-0/+18
On R-Car H3, some power areas (e.g. A3VP) contain I/O devices, which are also part of the CPG/MSSR Clock Domain. On all R-Car SoCs, devices in the "always-on" PM Domain are part of the Clock Domain served by the CPG/MSSR or CPG/MSTP driver. Hook up the CPG/MSTP or CPG/MSSR Clock Domain attach/detach callbacks to enable power management using module clocks. Which callback to hook up depends on the presence of device nodes compatible with "renesas,cpg-mstp-clocks". This clears the path for a future migration from the CPG/MSTP to the CPG/MSSR driver on R-Car H1 and Gen2. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2016-04-26soc: brcmstb: Unmap sun_top_ctrl_base on errorsFlorian Fainelli1-3/+11
Do not leak a ioremap()'d cookie around, unmaping it in case of errors Fixes: cef4bafcea2c ("soc: brcmstb: add SoC driver to brcmstb") Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2016-04-26soc: brcmstb: select SOC_BUSArnd Bergmann1-0/+1
The newly added code for the SoC bus fails to link if the bus is not built: drivers/soc/built-in.o: In function `brcmstb_soc_device_init': :(.init.text+0x110): undefined reference to `soc_device_register' This adds a 'select' statement to avoid the error. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Fixes: cef4bafcea2c ("soc: brcmstb: add SoC driver to brcmstb") Acked-by: Florian Fainelli <f.fainelli@gmail.com>
2016-04-25Merge tag 'qcom-soc-for-4.7-2' of ↵Arnd Bergmann4-13/+29
git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux into next/drivers Merge "Qualcomm ARM Based SoC Updates for v4.7 part 2" from Andy Gross: * Change SMD callback parameters * Use writecombine mapping for SMEM * tag 'qcom-soc-for-4.7-2' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux: soc: qcom: smd: Make callback pass channel reference soc: qcom: smem: Use write-combine remap for SMEM
2016-04-25Merge tag 'arm-soc/for-4.7/drivers' of http://github.com/Broadcom/stblinux ↵Arnd Bergmann1-0/+58
into next/drivers Merge "Broadcom ARM-based SoCs drivers changes" from Florian Fainelli: - Justin adds a soc_dev driver to properly report to user-space the Broadcom STB SoC family, product and revision - Florian reworks how the brcmstb_gisb driver dependency is done to enable it on Broadcom STB MIPS-based SoCs and remove a select in arch/arm/mach-bcm/Kconfig * tag 'arm-soc/for-4.7/drivers' of http://github.com/Broadcom/stblinux: bus: brcmstb_gisb: Rework dependencies soc: brcmstb: add SoC driver to brcmstb
2016-04-25Merge tag 'tegra-for-4.7-soc' of ↵Arnd Bergmann1-55/+95
git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/drivers Merge "soc/tegra: Changes for v4.7-rc1" from Thierry Reding: This contains a bunch of preparatory patches to the PMC driver which are a prerequisite to moving the driver to generic power domains. * tag 'tegra-for-4.7-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: dt-bindings: Update NVIDIA PMC for Tegra soc/tegra: pmc: Wait for powergate state to change soc/tegra: pmc: Ensure GPU partition can be toggled on/off by PMC soc/tegra: pmc: Remove additional check for a valid partition soc/tegra: pmc: Fix verification of valid partitions soc/tegra: pmc: Fix testing of powergate state soc/tegra: pmc: Change powergate and rail IDs to be an unsigned type soc/tegra: pmc: Protect public functions from potential race conditions soc/tegra: pmc: Restore base address on probe failure soc/tegra: pmc: Remove non-existing L2 partition for Tegra124 soc/tegra: pmc: Remove non-existing power partitions for Tegra210 soc/tegra: pmc: Remove debugfs entry on probe failure soc/tegra: pmc: Fix sparse warning for tegra_pmc_init_tsense_reset() soc/tegra: pmc: Add missing structure members to kernel-doc
2016-04-22soc: renesas: rcar-sysc: Make rcar_sysc_power_is_off() staticGeert Uytterhoeven1-1/+1
As of commit b12ff41658171f53 ("ARM: shmobile: r8a7779: Remove legacy PM Domain remainings"), rcar_sysc_power_is_off() is no longer used from SoC-specific code. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2016-04-22soc: renesas: rcar-sysc: Add DT support for SYSC PM domainsGeert Uytterhoeven2-1/+254
Populate the SYSC PM domains from DT, based on the presence of a device node for the System Controller. The actual power area hiearchy, and features of specific areas are obtained from tables in the C code. The SYSCIER and SYSCIMR register values are derived from the power areas present, which will help to get rid of the hardcoded values in R-Car H1 and R-Car Gen2 platform code later. Initialization is done from an early_initcall(), to make sure the PM Domains are initialized before secondary CPU bringup. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2016-04-22soc: renesas: rcar-sysc: Improve rcar_sysc_power() debug infoGeert Uytterhoeven1-1/+1
Print requested power domain state. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2016-04-22soc: renesas: Move pm-rcar to drivers/soc/renesas/rcar-syscGeert Uytterhoeven3-1/+171
Move the pm-rcar driver from arch/arm/mach-shmobile/ to drivers/soc/renesas/, and its header file to include/linux/soc/renesas/, so it can be shared between arm32 (R-Car H1 and Gen2) and arm64 (R-Car Gen3). Rename it to rcar-sysc as it's really a driver for the R-Car System Controller (SYSC). Kill the intermediate PM_RCAR config symbol, as it's not user configurable anymore, and to prepare for SoC-specific make rules. Add the missing #include <linux/types.h> to rcar-sysc.h, which was exposed by different include order. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2016-04-21soc: rockchip: power-domain: support qos save and restoreElaine Zhang1-3/+102
support qos save and restore when power domain on/off. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-04-20soc: mediatek: PMIC wrap: add MT2701/7623 supportJohn Crispin1-0/+154
Add the registers, callbacks and data structures required to make the wrapper work on MT2701 and MT7623. Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2016-04-20soc: mediatek: PMIC wrap: add mt6323 slave supportJohn Crispin1-0/+43
Add support for MT6323 slaves. This PMIC can be found on MT2701 and MT7623 EVB. The only function that we need to touch is pwrap_init_cipher(). Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2016-04-20soc: mediatek: PMIC wrap: add a slave specific structJohn Crispin1-47/+112
This patch adds a new struct pwrap_slv_type that we use to store the slave specific data. The patch adds 2 new helper functions to access the dew registers. The slave type is looked up via the wrappers child node. Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2016-04-20soc: mediatek: PMIC wrap: remove pwrap_is_mt8135() and pwrap_is_mt8173()John Crispin1-16/+12
With more SoCs being added the list of helper functions like these would grow. To mitigate this problem we remove the existing helpers and change the code to test against the pmic type stored inside the pmic specific datastructure that our context structure points at. There is one usage of pwrap_is_mt8135() that is ambiguous as the test should not be dependent on mt8135, but rather on the existence of a bridge. Add a new element to pmic_wrapper_type to indicate if a bridge is present and use this where appropriate. Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2016-04-20soc: mediatek: PMIC wrap: move wdt_src into the pmic_wrapper_type structJohn Crispin1-4/+5
Different SoCs will use different bitmask for the wdt_src. This patch defines the bitmask in the pmic_wrapper_type struct. This allows us to support new SoCs with a different bitmask to the one currently used. Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2016-04-20soc: mediatek: PMIC wrap: SPI_WRITE needs a different bitmask for MT2701/7623John Crispin1-4/+7
Different SoCs will use different bitmask for the SPI_WRITE command. This patch defines the bitmask in the pmic_wrapper_type struct. This allows us to support new SoCs with a different bitmask to the one currently used. Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2016-04-20soc: mediatek: PMIC wrap: WRAP_INT_EN needs a different bitmask for MT2701/7623John Crispin1-1/+4
MT2701 and MT7623 use a different bitmask for PWRAP_INT_EN. Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2016-04-20soc: mediatek: PMIC wrap: split SoC specific init into callbackJohn Crispin1-25/+42
This patch moves the SoC specific wrapper init code into separate callback to avoid pwrap_init() getting too large. This is done by adding a new element called init_special to pmic_wrapper_type. Each currently supported SoC gets its own version of the callback and we copy the code that was previously inside pwrap_init() to these new callbacks. Finally we point the 2 instances of pmic_wrapper_type at the 2 new functions. Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2016-04-20soc: mediatek: PMIC wrap: add wrapper callbacks for init_reg_clockJohn Crispin1-32/+38
Split init_reg_clock up into SoC specific callbacks. The patch also reorders the code to avoid the need for callback function prototypes. Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2016-04-20soc: mediatek: PMIC wrap: don't duplicate the wrapper dataJohn Crispin1-14/+8
As we add support for more devices struct pmic_wrapper_type will grow and we do not really want to start duplicating all the elements in struct pmic_wrapper. Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2016-04-20soc: qcom: spm: Use const and __initconst for qcom_cpuidle_opsJisheng Zhang1-1/+1
The qcom_cpuidle_ops structures is not over-written, so add "const" qualifier and replace __initdata with __initconst. Signed-off-by: Jisheng Zhang <jszhang@marvell.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Acked-by: Andy Gross <andy.gross@linaro.org>
2016-04-19soc: qcom: smd: Make callback pass channel referenceBjorn Andersson3-11/+28
By passing the smd channel reference to the callback, rather than the smd device, we can open additional smd channels from sub-devices of smd devices. Also updates the two smd clients today found in mainline. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2016-04-19soc: qcom: smem: Use write-combine remap for SMEMBjorn Andersson1-2/+1
Mapping the SMEM region as write combine makes the contiguous writes in SMD perform better and also allows us to do unaligned read and writes on ARM64. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Andy Gross <andy.gross@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2016-04-18soc: brcmstb: add SoC driver to brcmstbJustin Chen1-0/+58
Value of soc_dev_attributes: * family = chip family id * soc_id = product id * revision = product revision Signed-off-by: Justin Chen <justin.chen@broadcom.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2016-04-13Merge tag 'v4.7-rockchip-drivers-1' of ↵Olof Johansson1-5/+137
git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into next/drivers Rockchip soc-specific driver changes containing support for the rk3399 powerdomains and necessary infrastructure changes to accomodate them - like supporting nested powerdomains here. * tag 'v4.7-rockchip-drivers-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: soc: rockchip: power-domain: check the existing of regmap soc: rockchip: power-domain: Modify power domain driver for rk3399 dt-bindings: add binding for rk3399 power domains dt-bindings: add power-domain header for RK3399 SoCs soc: rockchip: power-domain: add support for sub-power domains soc: rockchip: power-domain: allow domains only handling idle requests soc: rockchip: power-domain: make idle handling optional Signed-off-by: Olof Johansson <olof@lixom.net>
2016-04-13Revert "soc: mediatek: SCPSYS: Fix double enabling of regulators"James Liao1-5/+6
This reverts commit cc8ed76938b5cf6a54ab3d60edabaf808dc960d1 ("soc: mediatek: SCPSYS: Fix double enabling of regulators") [1]. This patch fixes mt8173-evb failing boot issue. With commit [1], genpd state will not sync to real power domain state. So some resources such as clocks and regulators may stay in a wrong state. There is no regulator double enabling issue on mainline kernel, so we can refert commit [1] safely. Signed-off-by: James Liao <jamesjj.liao@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2016-04-12ARM: tegra: Remove redundant ARM_L1_CACHE_SHIFT_6 selectMasahiro Yamada1-2/+0
These two are both ARMv7 SoCs. They need not explicitly select ARM_L1_CACHE_SHIFT_6 because it is enabled along with CPU_V7. Refer to commit a092f2b15399 ("ARM: 7291/1: cache: assume 64-byte L1 cachelines for ARMv7 CPUs"). Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-04-12soc: rockchip: power-domain: check the existing of regmapShawn Lin1-0/+4
Check return value of syscon_node_to_regmap for rockchip_pm_domain_probe. If err value is returned, probe procedure should abort. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-04-05soc/tegra: pmc: Wait for powergate state to changeJon Hunter1-1/+8
Currently, the function tegra_powergate_set() simply sets the desired powergate state but does not wait for the state to change. In most cases we should wait for the state to change before proceeding. Currently, there is a case for Tegra114 and Tegra124 devices where we do not wait when starting the secondary CPU as this is not necessary. However, this is only done at boot time and so waiting here will only have a small impact on boot time. Therefore, update tegra_powergate_set() to wait when setting the powergate. By adding this feature, we can also eliminate the polling loop from tegra30_boot_secondary(). A function has been added for checking the status of the powergate and so update the tegra_powergate_is_powered() to use this macro as well. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-04-05soc/tegra: pmc: Ensure GPU partition can be toggled on/off by PMCJon Hunter1-1/+7
For Tegra124 and Tegra210, the GPU partition cannot be toggled on and off via the APBDEV_PMC_PWRGATE_TOGGLE_0 register. For these devices, the partition is simply powered up and down via an external regulator. For these devices, there is a separate register for controlling the signal clamping of the partition and this is described in the PMC SoC data by the "has_gpu_clamp" variable. Use this variable to determine if the GPU partition can be controlled via the APBDEV_PMC_PWRGATE_TOGGLE_0 register and ensure that no one can incorrectly try to toggle the GPU partition via the APBDEV_PMC_PWRGATE_TOGGLE_0 register. Furthermore, we cannot use the APBDEV_PMC_PWRGATE_STATUS_0 register to determine if the GPU partition is powered for Tegra124 and Tegra210. However, if the GPU partition is powered, then the signal clamp for the GPU partition should be removed and so use bit 0 of the APBDEV_PMC_GPU_RG_CNTRL_0 register to determine if the clamp has been removed (bit[0] = 0) and the GPU partition is powered. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-04-05soc/tegra: pmc: Remove additional check for a valid partitionJon Hunter1-2/+4
The function tegra_powergate_is_powered() verifies that the partition being queried is valid and so there is no need to check this before calling tegra_powergate_is_powered() in powergate_show(). So remove this extra check. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-04-05soc/tegra: pmc: Fix verification of valid partitionsJon Hunter1-4/+9
The Tegra power partitions are referenced by numerical IDs which are the same values programmed into the PMC registers for controlling the partition. For a given device, the valid partition IDs may not be contiguous and so simply checking that an ID is not greater than the maximum ID supported may not mean it is valid. Fix this by checking if the powergate is defined in the list of powergates for the Tegra SoC. Add a helper function for checking valid powergates and use where we need to verify if the powergate ID is valid or not. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-04-05soc/tegra: pmc: Fix testing of powergate stateJon Hunter1-8/+9
In tegra_powergate_set() the state of the powergates is read and OR'ed with the bit for the powergate of interest. This unsigned 32-bit value is then compared with a boolean value to test if the powergate is already in the desired state. When turning on a powergate, apart from the powergate that is represented by bit 0, this test will always return false and so we may attempt to turn on the powergate when it is already on. After OR'ing the bit for the powergate, check if the result is not equal to zero before comparing with the boolean value. Add a helper function to return the current state of a powergate and use this in both tegra_powergate_set() and tegra_powergate_is_powered() where we check the powergate status. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-04-05soc/tegra: pmc: Change powergate and rail IDs to be an unsigned typeJon Hunter1-18/+18
The Tegra powergate and rail IDs are always positive values and so change the type to be unsigned and remove the tests to see if the ID is less than zero. Update the Tegra DC powergate type to be an unsigned as well. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-04-05soc/tegra: pmc: Protect public functions from potential race conditionsJon Hunter1-14/+33
The PMC base address pointer is initialised during early boot so that early platform code may used the PMC public functions. During the probe of the PMC driver the base address pointer is mapped again and the initial mapping is freed. This exposes a window where a device accessing the PMC registers via one of the public functions, could race with the updating of the pointer and lead to a invalid access. Furthermore, the only protection between multiple devices attempting to access the PMC registers is when setting the powergate state to on or off. None of the other public functions that access the PMC registers are protected. Use the existing mutex to protect paths that may race with regard to accessing the PMC registers. Note that functions tegra_io_rail_prepare()/poll() either return a negative value on failure or zero on success. Therefore, it is not necessary to check if the return value is less than zero and so only test that the return value is not zero to test for failure. This simplifies the error handling with the mutex locking in place. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-04-05soc/tegra: pmc: Restore base address on probe failureJon Hunter1-6/+8
During early initialisation, the PMC registers are mapped and the PMC SoC data is populated in the PMC data structure. This allows other drivers access the PMC register space, via the public Tegra PMC APIs, prior to probing the PMC device. When the PMC device is probed, the PMC registers are mapped again and if successful the initial mapping is freed. If the probing of the PMC device fails after the registers are remapped, then the registers will be unmapped and hence the pointer to the PMC registers will be invalid. This could lead to a potential crash, because once the PMC SoC data pointer is populated, the driver assumes that the PMC register mapping is also valid and a user calling any of the public Tegra PMC APIs could trigger an exception because these APIs don't check that the mapping is still valid. Fix this by updating the mapping and freeing the original mapping only if probing the PMC device is successful. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-04-05soc/tegra: pmc: Remove non-existing L2 partition for Tegra124Jon Hunter1-1/+0
Tegra124 does not have an L2 power partition and the L2 cache is part of the cluster 0 non-CPU (CONC) partition. Remove the L2 as a valid partition for Tegra124. The TRM also shows that there is no L2 partition for Tegra124. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-04-05soc/tegra: pmc: Remove non-existing power partitions for Tegra210Jon Hunter1-4/+0
The power partitions L2, HEG, CELP and C1NC do not exist on Tegra210 but were incorrectly documented in the TRM. These will be removed from the TRM and so also remove their definitions. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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