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path: root/drivers/clk
AgeCommit message (Expand)AuthorFilesLines
2017-11-02clk: clk-gpio: Make GPIO clock provider use descriptors onlyLinus Walleij1-55/+35
2017-11-02clk: mediatek: add clock support for MT7622 SoCSean Wang6-0/+1334
2017-11-02clk: mediatek: add the option for determining PLL source clockChen Zhong2-1/+5
2017-11-02clk: mediatek: mark mtk_infrasys_init_early __initArnd Bergmann1-1/+1
2017-11-02clk: mediatek: Add MT2712 clock supportweiyi.lu@mediatek.com12-2/+2180
2017-11-02clk: imx: imx7d: Remove ARM_M0 clockAdriana Reus1-9/+0
2017-11-02clk: imx: imx7d: Fix parent clock for OCRAM_CLKAdriana Reus1-1/+1
2017-11-02clk: imx: clk-imx6ul: allow lcdif_pre_sel to change parent ratePhilipp Zabel1-1/+1
2017-11-02clk: imx6: refine hdmi_isfr's parent to make HDMI work on i.MX6 SoCs w/o VPUSébastien Szymanski1-1/+1
2017-11-02clk: qcom: clk-smd-rpm: add msm8996 rpmclksRajendra Nayak1-0/+82
2017-11-01clk: qcom: Implement RPM clocks for MSM8660/APQ8060Linus Walleij1-0/+93
2017-11-01clk: qcom: Remove unused RCG opsGeorgi Djakov2-82/+0
2017-11-01clk: at91: utmi: set the mainck rateLudovic Desroches1-14/+81
2017-11-01clk: qcom: common: Migrate to devm_* APIs for resets and clk providersStephen Boyd1-24/+2
2017-11-01clk: Add devm_of_clk_add_hw_provider()/del_provider() APIsStephen Boyd1-0/+52
2017-11-01clk: make clk_init_data constBhumika Goyal6-55/+55
2017-11-01clk: imx: make clk_ops constBhumika Goyal4-5/+5
2017-11-01clk: mmp: make clk_ops constBhumika Goyal3-3/+3
2017-11-01clk: hisilicon: make clk_ops constBhumika Goyal3-4/+4
2017-11-01clk: mxs: make clk_ops constBhumika Goyal2-2/+2
2017-11-01clk: sirf: make clk_ops constBhumika Goyal1-6/+6
2017-11-01clk: spear: make clk_ops constBhumika Goyal4-5/+5
2017-11-01CLK: SPEAr: make aux_clk_masks structures constBhumika Goyal3-3/+3
2017-11-01CLK: SPEAr: make structure field and function argument as constBhumika Goyal2-3/+3
2017-11-01clk: sunxi: explicitly request exclusive reset controlPhilipp Zabel1-1/+1
2017-11-01clk: sunxi: fix build warningCorentin LABBE1-2/+0
2017-11-01clk: hi6220: mark clock cs_atb_syspll as criticalLeo Yan1-1/+1
2017-11-01clk: tegra: Use readl_relaxed_poll_timeout_atomic() in tegra210_clock_init()Nicolin Chen1-2/+2
2017-11-01clk: tegra: dfll: Fix drvdata overwriting issueNicolin Chen3-13/+11
2017-11-01clk: tegra: Fix cclk_lp divisor registerMichał Mirosław1-1/+1
2017-11-01clk: tegra: Bump SCLK clock rate to 216 MHzDmitry Osipenko1-1/+1
2017-11-01clk: tegra: Use common definition of APBDMA clock gateDmitry Osipenko1-5/+1
2017-11-01clk: tegra: Correct parent of the APBDMA clockDmitry Osipenko1-1/+1
2017-11-01clk: tegra: Add AHB DMA clock entryDmitry Osipenko4-0/+4
2017-11-01clk: tegra: Mark APB clock as criticalJon Hunter1-1/+1
2017-10-31Merge tag 'v4.15-rockchip-clk-1' of git://git.kernel.org/pub/scm/linux/kernel...Stephen Boyd3-9/+7
2017-10-31Merge tag 'clk-renesas-for-v4.15-tag2' of git://git.kernel.org/pub/scm/linux/...Stephen Boyd13-34/+214
2017-10-31Merge tag 'meson-clk-for-4.15' of git://github.com/baylibre/clk-meson into cl...Stephen Boyd2-1/+297
2017-10-31Merge tag 'sunxi-clk-for-4.15' of https://git.kernel.org/pub/scm/linux/kernel...Stephen Boyd16-77/+451
2017-10-30Merge tag 'clk-v4.15-exynos-pm' of git://git.kernel.org/pub/scm/linux/kernel/...Stephen Boyd4-9/+206
2017-10-25Merge tag 'clk-v4.15-samsung' of git://git.kernel.org/pub/scm/linux/kernel/gi...Stephen Boyd10-190/+62
2017-10-25Merge tag 'clk-renesas-for-v4.15-tag1' of git://git.kernel.org/pub/scm/linux/...Stephen Boyd7-5/+213
2017-10-24clk: uniphier: fix clock data for PXs3Masahiro Yamada1-3/+3
2017-10-20clk: renesas: rcar-gen3: Restore R clock during resumeGeert Uytterhoeven1-2/+11
2017-10-20clk: renesas: rcar-gen3: Restore SDHI clocks during resumeGeert Uytterhoeven1-13/+50
2017-10-20clk: renesas: div6: Restore clock state during resumeGeert Uytterhoeven3-4/+40
2017-10-20clk: renesas: cpg-mssr: Add support to restore core clocks during resumeGeert Uytterhoeven6-11/+23
2017-10-20clk: renesas: cpg-mssr: Restore module clocks during resumeGeert Uytterhoeven1-0/+84
2017-10-20clk: renesas: cpg-mssr: Add du1 clock to R8A7745Fabrizio Castro1-0/+1
2017-10-20clk: renesas: rz: clk-rz is meant for RZ/A1Geert Uytterhoeven1-1/+1