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path: root/drivers/clk
AgeCommit message (Expand)AuthorFilesLines
2021-06-27drivers: ti: remove redundant error message in adpll.cYu Jiahua1-4/+1
2021-06-27clk: st: clkgen-fsyn: embed soc clock outputs within compatible dataAlain Volmat1-12/+101
2021-06-27clk: st: clkgen-pll: embed soc clock outputs within compatible dataAlain Volmat1-14/+106
2021-06-27clk: st: flexgen: embed soc clock outputs within compatible dataAlain Volmat1-14/+353
2021-06-27clk: st: clkgen-pll: remove unused variable of struct clkgen_pllAlain Volmat1-1/+0
2021-06-27clk: ingenic: Add support for the JZ4760Paul Cercueil4-0/+441
2021-06-27clk: ingenic: Support overriding PLLs M/N/OD calc algorithmPaul Cercueil2-13/+30
2021-06-27clk: ingenic: Remove pll_info.no_bypass_bitPaul Cercueil3-8/+6
2021-06-27clk: ingenic: Read bypass register only when there is onePaul Cercueil1-8/+11
2021-06-27clk: Support bypassing dividersPaul Cercueil5-29/+42
2021-06-27clk: qcom: clk-alpha-pll: fix CAL_L write in alpha_pll_fabia_prepareJonathan Marek1-1/+1
2021-06-27clk: actions: Add NIC and ETHERNET clock support for Actions S500 SoCCristian Ciocaltea1-1/+16
2021-06-27clk: actions: Fix AHPPREDIV-H-AHB clock chain on Owl S500 SoCCristian Ciocaltea1-8/+11
2021-06-27clk: actions: Fix bisp_factor_table based clocks on Owl S500 SoCCristian Ciocaltea1-15/+29
2021-06-27clk: actions: Fix SD clocks factor table on Owl S500 SoCCristian Ciocaltea1-4/+2
2021-06-27clk: actions: Fix UART clock dividers on Owl S500 SoCCristian Ciocaltea1-6/+6
2021-06-27clk: bd718xx: Drop BD70528 supportMatti Vaittinen2-12/+5
2021-06-27clk: stm32mp1: move RCC reset controller into RCC clock driverGabriel Fernandez1-13/+144
2021-06-27clk: stm32mp1: convert to module driverGabriel Fernandez1-43/+78
2021-06-27clk: stm32mp1: remove intermediate pll clocksGabriel Fernandez1-23/+42
2021-06-27clk: stm32mp1: merge 'ck_hse_rtc' and 'ck_rtc' into one clockGabriel Fernandez1-6/+48
2021-06-27clk: stm32mp1: merge 'clk-hsi-div' and 'ck_hsi' into one clockGabriel Fernandez1-5/+5
2021-06-27clk: lmk04832: add support for digital delayLiam Beguin1-6/+315
2021-06-27clk: add support for the lmk04832Liam Beguin3-0/+1296
2021-06-27clk: socfpga: clk-pll: Remove unused variable 'rc'Jian Xin1-2/+1
2021-06-27clk: qcom: Add camera clock controller driver for SM8250Jonathan Marek3-0/+2464
2021-06-27clk: qcom: clk-alpha-pll: add support for zonda pllJonathan Marek2-0/+180
2021-06-27clk/qcom: Remove unused variablesPu Lehui1-23/+0
2021-06-27clk: qcom: smd-rpmcc: Add support for MSM8226 rpm clocksBartosz Dudziak1-0/+1
2021-06-27clk: qcom: gcc: Add support for Global Clock controller found on MSM8226Bartosz Dudziak1-7/+162
2021-06-27clk: qcom: Add SM6125 (TRINKET) GCC driverKonrad Dybcio3-0/+4198
2021-06-27clk: qcom: gcc: Add support for a new frequency for SC7280Taniya Das1-0/+1
2021-06-27clk: agilex/stratix10/n5x: fix how the bypass_reg is handledDinh Nguyen1-3/+8
2021-06-27clk: agilex/stratix10: add support for the 2nd bypassDinh Nguyen3-2/+123
2021-06-27clk: agilex/stratix10: fix bypass representationDinh Nguyen2-21/+91
2021-06-27clk: agilex/stratix10: remove noc_clkDinh Nguyen2-34/+30
2021-06-25clk: tegra: clk-tegra124-dfll-fcpu: don't use devm functions for regulatorAlexandru Ardelean1-2/+2
2021-06-25clk: zynqmp: pll: Remove some dead codeChristophe JAILLET1-2/+0
2021-06-25clk: zynqmp: fix compile testing without ZYNQMP_FIRMWAREMichal Simek2-8/+24
2021-06-22clk: keystone: syscon-clk: Add support for AM64 specific epwm-tbclkLokesh Vutla1-0/+17
2021-06-14clk: imx8mq: remove SYS PLL 1/2 clock gatesLucas Stach1-38/+18
2021-06-14clk: imx: scu: Do not enable runtime PM for CPU clksNitin Garg1-12/+18
2021-06-14clk: imx: scu: add parent save and restoreDong Aisheng1-1/+28
2021-06-14clk: imx: scu: Only save DC SS clock using non-cached clock rateAnson Huang1-1/+8
2021-06-14clk: imx: scu: Add A72 frequency scaling supportAnson Huang1-1/+3
2021-06-14clk: imx: scu: Add A53 frequency scaling supportAnson Huang1-2/+2
2021-06-14clk: imx: scu: bypass pi_pll enable status restoreDong Aisheng1-1/+1
2021-06-14clk: imx: scu: detach pd if can't power upDong Aisheng1-0/+1
2021-06-14clk: imx: scu: bypass cpu clock save and restoreDong Aisheng1-0/+10
2021-06-14clk: imx: scu: add parallel port clock opsGuoniu.zhou1-0/+8