summaryrefslogtreecommitdiff
path: root/arch/riscv
AgeCommit message (Expand)AuthorFilesLines
2018-10-31mm: remove CONFIG_HAVE_MEMBLOCKMike Rapoport1-1/+0
2018-10-31mm: remove CONFIG_NO_BOOTMEMMike Rapoport1-1/+0
2018-10-31treewide: remove current_text_addrNick Desaulniers1-6/+0
2018-10-25Merge tag 'riscv-for-linus-4.20-mw0' of git://git.kernel.org/pub/scm/linux/ke...Linus Torvalds27-238/+679
2018-10-25Merge branch 'timers-core-for-linus' of git://git.kernel.org/pub/scm/linux/ke...Linus Torvalds1-0/+1
2018-10-24Merge branch 'siginfo-linus' of git://git.kernel.org/pub/scm/linux/kernel/git...Linus Torvalds2-24/+1
2018-10-22RISC-V: SMP cleanup and new featuresPalmer Dabbelt10-62/+245
2018-10-22RISC-V: Fix some RV32 bugs and build failuresPalmer Dabbelt4-2/+7
2018-10-22riscv: Add support to no-FPU systemsPalmer Dabbelt9-127/+196
2018-10-22RISC-V: Cosmetic menuconfig changesNick Kossifidis2-36/+39
2018-10-22riscv: move GCC version check for ARCH_SUPPORTS_INT128 to KconfigMasahiro Yamada2-2/+1
2018-10-22RISC-V: remove the unused return_to_handler exportChristoph Hellwig1-1/+0
2018-10-22RISC-V: Add futex support.Jim Wilson3-1/+129
2018-10-22RISC-V: Add FP register ptrace support for gdb.Jim Wilson2-0/+55
2018-10-22RISC-V: Mask out the F extension on systems without DPalmer Dabbelt1-0/+7
2018-10-22RISC-V: Don't set cacheinfo.{physical_line_partition,attributes}Palmer Dabbelt1-7/+0
2018-10-22RISC-V: Show IPI statsAnup Patel3-7/+49
2018-10-22RISC-V: Show CPU ID and Hart ID separately in /proc/cpuinfoAnup Patel1-4/+6
2018-10-22RISC-V: Use Linux logical CPU number instead of hartidAtish Patra6-25/+58
2018-10-22RISC-V: Add logical CPU indexing for RISC-VAtish Patra3-1/+46
2018-10-22RISC-V: Use WRITE_ONCE instead of direct accessAtish Patra1-2/+3
2018-10-22RISC-V: Use mmgrab()Palmer Dabbelt1-1/+2
2018-10-22RISC-V: Rename im_okay_therefore_i_am to found_boot_cpuPalmer Dabbelt1-4/+5
2018-10-22RISC-V: Rename riscv_of_processor_hart to riscv_of_processor_hartidPalmer Dabbelt3-4/+7
2018-10-22RISC-V: Provide a cleaner raw_smp_processor_id()Palmer Dabbelt1-10/+4
2018-10-22RISC-V: Disable preemption before enabling interruptsAtish Patra1-1/+5
2018-10-22RISC-V: Comment on the TLB flush in smp_callin()Palmer Dabbelt1-0/+4
2018-10-22RISC-V: Filter ISA and MMU values in cpuinfoPalmer Dabbelt1-7/+61
2018-10-22RISC-V: Don't set cacheinfo.{physical_line_partition,attributes}Palmer Dabbelt1-7/+0
2018-10-22RISC-V: No need to pass scause as arg to do_IRQ()Anup Patel2-3/+2
2018-10-22RISC-V: Avoid corrupting the upper 32-bit of phys_addr_t in ioremapVincent Chen1-1/+1
2018-10-22RISC-V: Select GENERIC_LIB_UMODDI3 on RV32Zong Li1-0/+1
2018-10-22RISC-V: Use swiotlb on RV64 onlyZong Li1-0/+3
2018-10-22RISC-V: Build tishift only on 64-bitZong Li1-1/+2
2018-10-22Auto-detect whether a FPU existsAlan Kao4-7/+19
2018-10-22Allow to disable FPU supportAlan Kao6-3/+29
2018-10-22Cleanup ISA string settingAlan Kao1-11/+8
2018-10-22Refactor FPU code in signal setup/return proceduresAlan Kao1-27/+41
2018-10-22Extract FPU context operations from entry.SAlan Kao3-87/+107
2018-10-03signal: Remove the need for __ARCH_SI_PREABLE_SIZE and SI_PAD_SIZEEric W. Biederman2-24/+1
2018-10-02RISCV: Fix end PFN for low memoryAtish Patra1-1/+1
2018-09-24RISC-V: include linux/ftrace.h in asm-prototypes.hJames Cowgill1-0/+7
2018-09-05RISC-V: Request newstat syscallsGuenter Roeck1-0/+1
2018-09-04riscv: Do not overwrite initrd_start and initrd_endGuenter Roeck1-7/+0
2018-08-28RISC-V: Use a less ugly workaround for unused variable warningsPalmer Dabbelt1-14/+1
2018-08-28riscv: tlb: Provide definition of tlb_flush() before including tlb.hWill Deacon1-0/+4
2018-08-25Merge tag 'kbuild-v4.19-2' of git://git.kernel.org/pub/scm/linux/kernel/git/m...Linus Torvalds1-2/+2
2018-08-24kbuild: rename LDFLAGS to KBUILD_LDFLAGSMasahiro Yamada1-2/+2
2018-08-20RISC-V: Fix sys_riscv_flush_icachePalmer Dabbelt4-9/+23
2018-08-20riscv: Delete asm/compat.hDeepa Dinamani2-29/+1
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-29 22:13:49 +0000