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AgeCommit message (Expand)AuthorFilesLines
2014-11-24MIPS: ralink: cleanup the soc specific pinmux dataJohn Crispin10-420/+294
2014-11-24MIPS: ralink: copy the commandline from the devicetreeJohn Crispin1-0/+2
2014-11-24MIPS: ralink: add a bootrom dumper moduleJohn Crispin2-0/+50
2014-11-24MIPS: ralink: add rt3883 wmac clockJohn Crispin1-0/+1
2014-11-24MIPS: ralink: add rt2880 wmac clockJohn Crispin1-1/+2
2014-11-24MIPS: ralink: add missing clk_set_rate() to clk.cJohn Crispin1-0/+6
2014-11-24MIPS: ralink: allow manual memory overrideJohn Crispin1-1/+15
2014-11-24MIPS: ralink: add illegal access driverJohn Crispin2-0/+89
2014-11-24MIPS: ralink: add rt_sysc_m32 helperJohn Crispin1-0/+7
2014-11-24MIPS: ralink: add a helper for reading the ECO versionJohn Crispin1-0/+5
2014-11-24MIPS: ralink: add verbose pmu infoJohn Crispin1-0/+26
2014-11-24MIPS: lantiq: add missing spi clock on falcon SoCJohn Crispin1-0/+2
2014-11-24MIPS: lantiq: the detection of the gpe clock is brokenJohn Crispin1-5/+4
2014-11-24MIPS: lantiq: copy the commandline from the devicetreeJohn Crispin1-0/+2
2014-11-24MIPS: lantiq: move eiu init after irq_domain registerJohn Crispin1-24/+24
2014-11-24MIPS: lantiq: export soc typeJohn Crispin2-0/+7
2014-11-24MIPS: lantiq: add support for xrx200 firmware depending on soc typeJohn Crispin1-1/+22
2014-11-24MIPS: lantiq: reboot gphy on restartJohn Crispin1-1/+8
2014-11-24MIPS: lantiq: add reset-controller api supportJohn Crispin2-0/+63
2014-11-24MIPS: lantiq: handle vmmc memory reservationJohn Crispin2-0/+71
2014-11-24MIPS: Alchemy: Remove direct access to prepare_count field of struct clkTomeu Vizoso1-4/+3
2014-11-24clocksource: mips-gic: Bump up rating of GIC timerAndrew Bresticker1-1/+1
2014-11-24clocksource: mips-gic: Use clockevents_config_and_registerAndrew Bresticker1-9/+1
2014-11-24clocksource: mips-gic: Use CPU notifiers to setup the timerAndrew Bresticker2-20/+45
2014-11-24clocksource: mips-gic: Use percpu_dev_idAndrew Bresticker1-3/+2
2014-11-24clocksource: mips-gic: Remove gic_event_handlerAndrew Bresticker1-5/+0
2014-11-24clocksource: mips-gic: Move gic_frequency to clocksource driverAndrew Bresticker4-2/+5
2014-11-24clocksource: mips-gic: Staticize local symbolsAndrew Bresticker1-5/+5
2014-11-24clocksource: mips-gic: Combine with GIC clockevent driverAndrew Bresticker6-119/+92
2014-11-24MIPS: Move GIC clocksource driver to drivers/clocksource/Andrew Bresticker7-9/+9
2014-11-24irqchip: mips-gic: Use GIC_SH_WEDGE_{SET,CLR} macrosAndrew Bresticker1-2/+2
2014-11-24irqchip: mips-gic: Remove gic_{pending,itrmask}_regsAndrew Bresticker1-13/+3
2014-11-24irqchip: mips-gic: Clean up #includesAndrew Bresticker1-5/+2
2014-11-24irqchip: mips-gic: Clean up header fileAndrew Bresticker2-104/+29
2014-11-24MAINTAINERS: Add entry for bcm63xx/bcm33xx UDC gadget driverKevin Cernekee1-0/+6
2014-11-24MAINTAINERS: Add entry for BCM33xx cable chipsKevin Cernekee1-0/+8
2014-11-24MIPS: bcm3384: Initial commit of bcm3384 platform supportKevin Cernekee13-0/+698
2014-11-24Documentation: DT: Add "mti" vendor prefixKevin Cernekee1-0/+1
2014-11-24Documentation: DT: Add entries for BCM3384 and its peripheralsKevin Cernekee4-0/+67
2014-11-24MIPS: Create a helper function for DT setupKevin Cernekee4-22/+22
2014-11-24MIPS: BMIPS: Add PRId for BMIPS5200 (Whirlwind)Kevin Cernekee2-0/+2
2014-11-24MIPS: BMIPS: Add special cache handling in c-r4k.cKevin Cernekee1-0/+43
2014-11-24MIPS: BMIPS: Let each platform customize the CPU1 IRQ maskKevin Cernekee2-2/+5
2014-11-24MIPS: BMIPS: Select the appropriate L1_CACHE_SHIFT for 438x and 5000 CPUsKevin Cernekee1-0/+2
2014-11-24MIPS: Allow MIPS_CPU_SCACHE to be used with different line sizesKevin Cernekee1-1/+1
2014-11-24MIPS: BMIPS: Explicitly configure reset vectors prior to secondary bootKevin Cernekee1-21/+8
2014-11-24MIPS: BMIPS: Mask off timer IRQs when hot-unplugging a CPUJon Fraser1-0/+1
2014-11-24MIPS: BMIPS: Allow BMIPS3300 to utilize SMP ebase relocation codeJon Fraser1-0/+1
2014-11-24MIPS: BMIPS: Introduce helper function to change the reset vectorKevin Cernekee1-7/+58
2014-11-24MIPS: BMIPS: Align secondary boot sequence with latest firmware releasesKevin Cernekee1-11/+1
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