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2017-02-08drm: Cancel drm_fb_helper_dirty_work on unloadChris Wilson1-0/+2
We can not allow the worker to run after its fbdev, or even the module, has been removed. Fixes: eaa434defaca ("drm/fb-helper: Add fb_deferred_io support") Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Noralf Trønnes <noralf@tronnes.org> Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Cc: Jani Nikula <jani.nikula@linux.intel.com> Cc: Sean Paul <seanpaul@chromium.org> Cc: dri-devel@lists.freedesktop.org Cc: <stable@vger.kernel.org> # v4.7+ Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Link: http://patchwork.freedesktop.org/patch/msgid/20170207124956.14954-1-chris@chris-wilson.co.uk
2017-02-08Merge branch 'drm-rockchip-next-2017-02-07' of ↵Dave Airlie1-1/+1
https://github.com/markyzq/kernel-drm-rockchip into drm-next Single compile fix. * 'drm-rockchip-next-2017-02-07' of https://github.com/markyzq/kernel-drm-rockchip: drm/rockchip: cdn-dp: fix cdn-dp complie warning
2017-02-07drm/rockchip: cdn-dp: fix cdn-dp complie warningMark Yao1-1/+1
fix warning: drivers/gpu/drm/rockchip/cdn-dp-reg.c:632:24: warning: 'val[1]' may be used uninitialized in this function [-Wmaybe-uninitialized] msa_misc = 2 * val[0] + 32 * val[1] + Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
2017-02-07Merge branch 'msm-next' of git://people.freedesktop.org/~robclark/linux into ↵Dave Airlie45-556/+2712
drm-next The big things this time around are: 1) support for hw cursor on newer mdp5 devices (snapdragon 820+, tested on db820c) 2) dsi encoder cleanup 3) gpu dt bindings cleanup so we can get the gpu nodes merged upstream * 'msm-next' of git://people.freedesktop.org/~robclark/linux: (32 commits) drm/msm: return -EFAULT if copy_from_user() fails drm/msm/dsi: Add PHY/PLL for 8x96 drm/msm/dsi: Add new method to calculate 14nm PHY timings drm/msm/dsi: Move PHY operations out of host drm/msm/dsi: Reset both PHYs before clock operation for dual DSI drm/msm/dsi: Pass down use case to PHY drm/msm/dsi: Return more timings from PHY to host drm/msm/dsi: Add a PHY op that initializes version specific stuff drm/msm/dsi: Add 8x96 info in dsi_cfg drm/msm/dsi: Don't error if a DSI host doesn't have a device connected drm/msm/mdp5: Add support for legacy cursor updates drm/msm/mdp5: Refactor mdp5_plane_atomic_check drm/msm/mdp5: Add cursor planes drm/msm/mdp5: Misc cursor plane bits drm/msm/mdp5: Configure COLOR3_OUT propagation drm/msm/mdp5: Use plane helpers to configure src/dst rectangles drm/msm/mdp5: Prepare CRTC/LM for empty stages drm/msm/mdp5: Create only as many CRTCs as we need drm/msm/mdp5: cfg: Change count to unsigned int drm/msm/mdp5: Create single encoder per interface (INTF) ...
2017-02-07Merge branch 'drm-rockchip-next-2017-02-05' of ↵Dave Airlie10-4/+2872
https://github.com/markyzq/kernel-drm-rockchip into drm-next rockchip CDN-DP support. * 'drm-rockchip-next-2017-02-05' of https://github.com/markyzq/kernel-drm-rockchip: drm/rockchip: cdn-dp: don't configure hardware in mode_set drm/rockchip: cdn-dp: retry to check sink count drm/rockchip: cdn-dp: Move mutex_init to probe drm/rockchip: cdn-dp: do not use drm_helper_hpd_irq_event drm/rockchip: cdn-dp: Do not run worker while suspended drm/rockchip: cdn-dp: Load firmware if no monitor connected drm/rockchip: cdn-dp: add cdn DP support for rk3399 drm/rockchip: return ERR_PTR instead of NULL drm/rockchip: vop: make vop register setting take effect
2017-02-07Merge tag 'drm-misc-next-2017-02-03' of ↵Dave Airlie96-818/+3546
git://anongit.freedesktop.org/git/drm-misc into drm-next Final 4.11 feature pull request: - sii8520 bridge update from Andrzej - ->release callback, maybe somewhen in the future we'll even get drm_device lifetimes correct! (Chris Wilson) - drm_mm search improvements, and good docs for different search strategies now (Chris) - simplify fbdev emulation init parameters (Gabriel) - bunch of misc things all over ... and the first few patches from our small driver in drm-misc experiment: - cleanups for qxl and bochs from a few different people - dsi support for vc4 (not yet the panel driver, that's under discussion still) from Eric - meson rename to meson-drm to distinguish from other platform drivers (Neil Amstrong) * tag 'drm-misc-next-2017-02-03' of git://anongit.freedesktop.org/git/drm-misc: (47 commits) drm: kselftest for drm_mm and bottom-up allocation drm: Improve drm_mm search (and fix topdown allocation) with rbtrees drm: Fix build when FBDEV_EMULATION is disabled drm: Rely on mode_config data for fb_helper initialization drm: Provide a driver hook for drm_dev_release() drm: meson: rename driver name to meson-drm drm: meson: rename module name to meson-drm drm/bridge/sii8620: enable interlace modes drm/bridge/sii8620: enable MHL3 mode if possible drm/bridge/sii8620: add HSIC initialization code drm/bridge/sii8620: improve gen2 write burst IRQ routine drm/bridge/sii8620: send EMSC features on request drm/bridge/sii8620: rewrite hdmi start sequence drm/bridge/mhl: add MHL3 infoframe related definitions drm/bridge/sii8620: fix disconnect sequence drm/bridge/sii8620: split EDID read and write code drm/bridge/sii8620: add delay during cbus reset drm/bridge/sii8620: do not stop MHL output when TMDS input is stopped drm/bridge/sii8620: set gen2 write burst before sending MSC command drm/bridge/sii8620: abstract out sink detection code ...
2017-02-06drm/msm: return -EFAULT if copy_from_user() failsDan Carpenter1-6/+7
copy_from_user_inatomic() is actually a local function that returns -EFAULT or positive values on error. Otherwise copy_from_user() returns the number of bytes remaining to be copied. We want to return -EFAULT here. I removed an unlikely() because we just did a copy_from_user() so I don't think it can possibly make a difference. Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-02-06drm/msm/dsi: Add PHY/PLL for 8x96Archit Taneja9-0/+1319
Extend the DSI PHY/PLL drivers to support the DSI 14nm PHY/PLL found on 8x96. These are picked up from the downstream driver. The PHY part is similar to the other DSI PHYs. The PLL driver requires some trickery so that one DSI PLL can drive both the DSIs (i.e, dual DSI mode). In the case of dual DSI mode. One DSI instance becomes the clock master, and other the clock slave. The master PLL's output (Byte and Pixel clock) is fed to both the DSI hosts/PHYs. When the DSIs are configured in dual DSI mode, the PHY driver communicates to the PLL driver using msm_dsi_pll_set_usecase() which instance is the master and which one is the slave. When setting rate, the master PLL also configures some of the slave PLL/PHY registers which need to be identical to the master's for correct dual DSI behaviour. There are 2 PLL post dividers that should have ideally been modelled as generic clk_divider clocks, but require some customization for dual DSI. In particular, when the master PLL's post-diviers are set, the slave PLL's post-dividers need to be set too. The clk_ops for these use clk_divider's helper ops and flags internally to prevent redundant code. Cc: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-02-06drm/msm/dsi: Add new method to calculate 14nm PHY timingsHai Li2-1/+127
The 14nm DSI PHY on 8x96 (called PHY v2 downstream) requires a different set of calculations for computing D-PHY timing params. Create a timing_calc_v2 func for the newer v2 PHYs. Signed-off-by: Hai Li <hali@codeaurora.org> Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-02-06drm/msm/dsi: Move PHY operations out of hostHai Li8-125/+172
Since DSI PHY has been a separate platform device, it should not depend on the resources in host to be functional. This change is to trigger PHY operations in manager, instead of host, so that host and PHY can be completely separated. Signed-off-by: Hai Li <hali@codeaurora.org> Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-02-06drm/msm/dsi: Reset both PHYs before clock operation for dual DSIArchit Taneja3-15/+43
In case of dual DSI, some registers in PHY1 have been programmed during PLL0 clock's set_rate. The PHY1 reset called by host1 later will silently reset those PHY1 registers. This change is to reset and enable both PHYs before any PLL clock operation. [Originally worked on by Hai Li <hali@codeaurora.org>. Fixed up by Archit Taneja <architt@codeaurora.org>] Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-02-06drm/msm/dsi: Pass down use case to PHYHai Li4-30/+51
For some new types of DSI PHY, more settings depend on use cases controlled by DSI manager. This change allows DSI manager to setup PHY with a use case. Signed-off-by: Hai Li <hali@codeaurora.org> Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-02-06drm/msm/dsi: Return more timings from PHY to hostHai Li5-27/+41
The DSI host is required to configure more timings calculated in PHY. By introducing a shared structure, this change allows more timing information passed from PHY to host. Signed-off-by: Hai Li <hali@codeaurora.org> Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-02-06drm/msm/dsi: Add a PHY op that initializes version specific stuffArchit Taneja5-9/+30
Create an init() op for dsi_phy which sets up things specific to a given DSI PHY. The dsi_phy driver probe expects every DSI version to get a "dsi_phy_regulator" mmio base. This isn't the case for 8x96. Creating an init() op will allow us to accommodate such differences. Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-02-06drm/msm/dsi: Add 8x96 info in dsi_cfgArchit Taneja2-0/+26
Add 8x96 DSI data in dsi_cfg. The downstream kernel's dsi_host driver enables core_mmss_clk. We're seeing some branch clock warnings on 8x96 when enabling this. There doesn't seem to be any negative effect with not enabling this clock, so use it once we figure out why we get the warnings. Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-02-06drm/msm/dsi: Don't error if a DSI host doesn't have a device connectedArchit Taneja1-5/+5
The driver returns an error if a DSI DT node is populated, but no device is connected to it or if the data-lane map isn't present. Ideally, such a DSI node shouldn't be probed at all (i.e, its status should be set to "disabled in DT"), but there isn't any harm in registering the DSI device even if it doesn't have a bridge/panel connected to it. Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-02-06drm/msm/mdp5: Add support for legacy cursor updatesArchit Taneja3-3/+115
This code has been more or less picked up from the vc4 and intel implementations of update_plane() funcs for cursor planes. The update_plane() func is usually the drm_atomic_helper_update_plane func that will issue an atomic commit with the plane updates. Such commits are not intended to be done faster than the vsync rate. The legacy cursor userspace API, on the other hand, expects the kernel to handle cursor updates immediately. Create a fast path in update_plane, which updates the cursor registers and flushes the configuration. The fast path is taken when there is only a change in the cursor's position in the crtc, or a change in the cursor's crop co-ordinates. For anything else, we go via the slow path. We take the slow path even when the fb changes, and when there is currently no fb tied to the plane. This should hopefully ensure that we always take a slow path for every new fb. This in turn should ensure that the fb is pinned/prepared. Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-02-06drm/msm/mdp5: Refactor mdp5_plane_atomic_checkArchit Taneja1-12/+20
In mdp5_plane_atomic_check, we get crtc_state from drm_plane_state. Later, for cursor planes, we'll populate the update_plane() func that takes a fast asynchronous path to implement cursor movements. There, we would need to call a similar atomic_check func to validate the plane state, but crtc_state would need to be derived differently. Refactor mdp5_plane_atomic_check to mdp5_plane_atomic_check_with_state such that the latter takes crtc_state as an argument. This is similar to what the intel driver has done for async cursor updates. Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-02-06drm/msm/mdp5: Add cursor planesArchit Taneja2-12/+26
Register cursor drm_planes. The loop in modeset_init that inits the planes and crtcs has to be refactored a bit. We first iterate all the hwpipes to find the cursor planes. Then, we loop again to create crtcs. In msm_atomic_wait_for_commit_done, remove the check which bypasses waiting for vsyncs if state->legacy_cursor_updates is true. We will later create a fast path for cursor position changes in the cursor plane's update_plane func that doesn't go via the regular atomic commit path. For rest of cursor related updates, we will have to wait for vsyncs, so ignore the legacy_cursor_updates flag. Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-02-06drm/msm/mdp5: Misc cursor plane bitsArchit Taneja8-13/+75
These are various changes added in preparation for cursor planes: - Add a pipe_cursor block for 8x96 in mdp5_cfg. - Add a new pipe CAP called MDP_PIPE_CAP_CURSOR. Use this to ensure we assign a cursor SSPP for a drm_plane with type DRM_PLANE_TYPE_CURSOR. - Update mdp5_ctl_blend_mask/ext_blend_mask funcs to incorporate cursor SSPPs. - In mdp5_ctl_blend, iterate through MAX_STAGES instead of stage_cnt, we need to do this because we can now have empty stages in between. - In mdp5_crtc_atomic_check, make sure that the cursor plane has the highest zorder, and stage the cursor plane to the maximum stage # present on the HW. - Create drm_crtc_funcs that doesn't try to implement cursors using the older LM cursor HW. - Pass drm_plane_type in mdp5_plane_init instead of a bool telling whether plane is primary or not. Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-02-06drm/msm/mdp5: Configure COLOR3_OUT propagationArchit Taneja1-0/+30
In MDP5 Layer Mixer HW, the blender output is only the blended color components (i.e R, G and B, or COLOR0/1/2 in MDP5 HW terminology). This is fed to the BG input of the next blender. We also need to provide an alpha (COLOR3) value for the BG input at the next stage. This is configured via using the REG_MDP5_LM_BLEND_COLOR_OUT register. For each stage, we can propagate either the BG or FG alpha to the next stage. The approach taken by the driver is to propagate FG alpha, if the plane staged on that blender has an alpha. If it doesn't, we try to propagate the base layer's alpha. This is borrowed from downstream MDP5 kernel driver. Without this, we don't see any cursor plane content. Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-02-06drm/msm/mdp5: Use plane helpers to configure src/dst rectanglesArchit Taneja2-19/+59
The MDP5 plane's atomic_check ops doesn't perform clipping tests. This didn't hurt us much in the past, but clipping becomes important with cursor planes. Use drm_plane_helper_check_state, the way rockchip/intel/mtk drivers already do. Use these drivers as reference. Clipping requires knowledge of the crtc width and height. This requires us to call drm_atomic_helper_check_modeset before drm_atomic_helper_check_planes in the driver's atomic_check op, because check_modetest will populate the mode for the crtc, needed to populate the clip rectangle. We update the plane_enabled(state) local helper to use state->visible, since state->visible and 'state->fb && state->crtc' represent the same thing. One issue with the existing code is that we don't have a way to disable the plane when it's completely clipped out. Until there isn't an update on the crtc (which would de-stage the plane), we would still see the plane in its last 'visible' configuration. Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-02-06drm/msm/mdp5: Prepare CRTC/LM for empty stagesArchit Taneja4-6/+6
Use SSPP_NONE in mdp5_plane_pipe() if there is now hwpipe allocated for the drm_plane. Returning '0' means we are returning VIG0 pipe. Also, use the mdp5_pipe enum to pass around the stage array. Initialize the stage to SSPP_NONE by default. We do the above because 1) Cursor plane has to be staged at the topmost blender of the LM, which can result in empty stages in between 2) In the future, when we support multiple LMs per CRTC. We could have stages which don't have any pipe assigned to them. Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-02-06drm/msm/mdp5: Create only as many CRTCs as we needArchit Taneja1-10/+29
We currently create CRTCs equaling to the # of Layer Mixer blocks we have on the MDP5 HW. This number is generally more than the # of encoders (INTFs) we have in the MDSS HW. The number of encoders connected to displays on the platform (as described by DT) would be even lesser. Create only N drm_crtcs, where N is the number of drm_encoders successfully registered. To do this, we call modeset_init_intf() before we init the drm_crtcs and drm_planes. Because of this change, setting encoder->possible_crtcs needs to be moved from construct_encoder() to a later point when we know how many CRTCs we have. Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-02-06drm/msm/mdp5: cfg: Change count to unsigned intArchit Taneja1-1/+1
Count can't be non-zero. Changing to uint will also prevent future warnings. Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-02-06drm/msm/mdp5: Create single encoder per interface (INTF)Archit Taneja4-156/+66
For the DSI interfaces, the mdp5_kms core creates 2 encoders for video and command modes. Create only a single encoder per interface. When creating the encoder, set the interface type to MDP5_INTF_MODE_NONE. It's the bridge (DSI/HDMI/eDP) driver's responsibility to set a different interface type. It can use the the kms func op set_encoder_mode to change the mode of operation, which in turn would configure the interface type for the INTF. In mdp5_cmd_encoder.c, we remove the redundant code, and make the commmand mode funcs as helpers that are used in mdp5_encoder.c Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-02-06drm/msm/mdp5: Prepare for merging video and command encodersArchit Taneja3-10/+28
Rename the mdp5_encoder_* ops for active displays to mdp5_vid_encoder_* ops. Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-02-06drm/msm: Set encoder's mode of operation using a kms funcArchit Taneja7-0/+69
The mdp5 kms driver currently sets up multiple encoders per interface (INTF), one for each kind of mode of operation it supports. We create 2 drm_encoders for DSI, one for Video Mode and the other for Command Mode operation. The reason behind this approach could have been that we aren't aware of the DSI device's mode of operation when we create the encoders. This makes things a bit complicated, since these encoders have to be further attached to the same DSI bridge. The easier way out is to create a single encoder, and make the DSI driver set its mode of operation when we know what the DSI device's mode flags are. Start with providing a way to set the mdp5_intf_mode using a kms func that sets the encoder's mode of operation. When constructing a DSI encoder, we set the mode of operation to Video Mode as default. When the DSI device is attached to the host, we probe the DSI mode flags and set the corresponding mode of operation. Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-02-06drm/msm: Construct only one encoder for DSIArchit Taneja6-67/+32
We currently create 2 encoders for DSI interfaces, one for command mode and other for video mode operation. This isn't needed as we can't really use both the encoders at the same time. It also makes connecting bridges harder. Switch to creating a single encoder. For now, we assume that the encoder is configured only in video mode. Later, the same encoder would be usable in both modes. Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-02-06drm/msm/dsi: Set msm_dsi->encoders before initializing bridgeArchit Taneja1-5/+3
The commit "drm: bridge: Link encoder and bridge in core code" updated the drm_bridge_attach() API to also include the drm_encoder pointer the bridge attaches to. The func msm_dsi_manager_bridge_init() now relies on the drm_encoder pointer stored in msm_dsi->encoders to pass the encoder to the bridge API. msm_dsi->encoders is unfortunately set after this function is called, resulting in us passing a NULL pointer to drm_brigde_attach. This results in an error and the DSI driver probe fails. Move the initialization of msm_dsi->encoders[] a bit up. Also, don't try to set the encoder's bridge. That's now managed by the bridge API. Cc: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-02-06drm/msm/dsi: Update generated headersArchit Taneja1-13/+256
Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-02-06drm/msm/mdp5: Update generated headersArchit Taneja1-23/+25
Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-02-06drm/msm/mdp5: cfg: Add pipe_cursor blockArchit Taneja1-0/+1
Define the block in advance so that the generated mdp5.xml.h doesn't break build. Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-02-06drm/msm: let gpu wire up it's own fault handlerRob Clark3-2/+31
Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-02-06drm/msm: drop _clk suffix from clk namesRob Clark4-10/+29
Suggested by Rob Herring. We still support the old names for compatibility with downstream android dt files. Cc: Rob Herring <robh@kernel.org> Signed-off-by: Rob Clark <robdclark@gmail.com> Reviewed-by: Eric Anholt <eric@anholt.net> Acked-by: Rob Herring <robh@kernel.org>
2017-02-06drm/msm: drop quirks bindingRob Clark4-20/+7
This was never documented or used in upstream dtb. It is used by downstream bindings from android device kernels. But the quirks are a property of the gpu revision, and as such are redundant to be listed separately in dt. Instead, move the quirks to the device table. Signed-off-by: Rob Clark <robdclark@gmail.com> Reviewed-by: Eric Anholt <eric@anholt.net>
2017-02-06drm/msm: drop qcom,chipidRob Clark3-6/+46
The original way we determined the gpu version was based on downstream bindings from android kernel. A cleaner way is to get the version from the compatible string. Note that no upstream dtb uses these bindings. But the code still supports falling back to the legacy bindings (with a warning), so that we are still compatible with the gpu dt node from android device kernels. Signed-off-by: Rob Clark <robdclark@gmail.com> Reviewed-by: Eric Anholt <eric@anholt.net> Acked-by: Rob Herring <robh@kernel.org>
2017-02-06drm/msm: remove qcom,gpu-pwrlevels bindingsRob Clark2-17/+4
The plan is to use the OPP bindings. For now, remove the documentation for qcom,gpu-pwrlevels, and make the driver fall back to a safe low clock if the node is not present. Note that no upstream dtb use this node. For now we keep compatibility with this node to avoid breaking compatibility with downstream android dt files. Signed-off-by: Rob Clark <robdclark@gmail.com> Reviewed-by: Eric Anholt <eric@anholt.net> Acked-by: Rob Herring <robh@kernel.org>
2017-02-05drm/rockchip: cdn-dp: don't configure hardware in mode_setChris Zhong1-25/+24
With atomic modesetting the hardware will be powered off when the mode_set function is called. We should configure the hardware in the enable function. Signed-off-by: Chris Zhong <zyw@rock-chips.com>
2017-02-05drm/rockchip: cdn-dp: retry to check sink countChris Zhong2-40/+52
Sometimes the Dock is disconnected, but cdn_dp_encoder_disable is not triggered by DRM. For example, unplug the Dock in console mode, and re-plug it again, the cdn_dp_event_work will try to get the sink count of Dock, since the DP is still active. But the Dock has been powered down, it need re-power on, and wait for a while until it is ready to DPCD communication. Signed-off-by: Chris Zhong <zyw@rock-chips.com>
2017-02-05drm/rockchip: cdn-dp: Move mutex_init to probeJeffy Chen1-1/+1
We're trying to lock mutex when cdn-dp shutdown, so we need to make sure the mutex is inited in cdn-dp's probe. Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> Reviewed-by: Guenter Roeck <groeck@chromium.org> Reviewed-by: Chris Zhong <zyw@rock-chips.com> Signed-off-by: Chris Zhong <zyw@rock-chips.com>
2017-02-05drm/rockchip: cdn-dp: do not use drm_helper_hpd_irq_eventChris Zhong1-1/+8
The cdn_dp_pd_event_work is using drm_helper_hpd_irq_event to update the connector status, this function is used to update all connectors of drm_device. Therefore, the detect of other connector will be call, when cdn_dp_pd_event_work is triggered, every time. It is not necessary, and it may cause system crash. replace drm_helper_hpd_irq_event with drm_kms_helper_hotplug_event, only update cdn-dp status. Signed-off-by: Chris Zhong <zyw@rock-chips.com> Tested-by: Guenter Roeck <groeck@chromium.org> Reviewed-by: Guenter Roeck <groeck@chromium.org>
2017-02-05drm/rockchip: cdn-dp: Do not run worker while suspendedGuenter Roeck2-2/+14
If the driver is in suspended mode, the dp block may be disabled, and chip registers may not be accessible. Yet, the worker may be triggered in this situation by an extcon event. If that happens, the following crash will be seen. cdn-dp fec00000.dp: [drm:cdn_dp_pd_event_work] *ERROR* Enable dp failed -19 cdn-dp fec00000.dp: [drm:cdn_dp_pd_event_work] Connected, not enabled. Enabling cdn Bad mode in Error handler detected, code 0xbf000002 -- SError CPU: 1 PID: 10357 Comm: kworker/1:2 Not tainted 4.4.21-05903-ge0514ea #1 Hardware name: Google Kevin (DT) Workqueue: events cdn_dp_pd_event_work task: ffffffc0cda67080 ti: ffffffc0b9b80000 task.ti: ffffffc0b9b80000 PC is at cdn_dp_clock_reset+0x30/0xa8 LR is at cdn_dp_enable+0x1e0/0x69c ... Call trace: [<ffffffc0005a7e24>] cdn_dp_pd_event_work+0x58/0x3f4 [<ffffffc0002397f0>] process_one_work+0x240/0x424 [<ffffffc00023a28c>] worker_thread+0x2fc/0x424 [<ffffffc00023f5fc>] kthread+0x10c/0x114 [<ffffffc000203dd0>] ret_from_fork+0x10/0x40 Problem is two-fold: The worker should not run while suspended, and the suspend function should not call cdn_dp_disable() while the worker is running. Signed-off-by: Guenter Roeck <groeck@chromium.org> Signed-off-by: Sean Paul <seanpaul@chromium.org> Signed-off-by: Chris Zhong <zyw@rock-chips.com>
2017-02-05drm/rockchip: cdn-dp: Load firmware if no monitor connectedGuenter Roeck1-6/+1
If no monitor is connected, suspend/resume cycles result in firmware load errors because the driver attempts to load the firmware while the system is in suspend state. This results in a kernel warning and traceback. Loading the firmware during boot fixes the problem. Note that we can not just call schedule_work conditionally in cdn_dp_pd_event() if the insertion status changed. The problem would still be seen if a monitor is connected for the first time during suspend. Signed-off-by: Guenter Roeck <groeck@chromium.org> Signed-off-by: Sean Paul <seanpaul@chromium.org> Signed-off-by: Chris Zhong <zyw@rock-chips.com>
2017-02-05drm/rockchip: cdn-dp: add cdn DP support for rk3399Chris Zhong9-3/+2842
Add support for cdn DP controller which is embedded in the rk3399 SoCs. The DP is compliant with DisplayPort Specification, Version 1.3, This IP is compatible with the rockchip type-c PHY IP. There is a uCPU in DP controller, it need a firmware to work, please put the firmware file to /lib/firmware/rockchip/dptx.bin. The uCPU in charge of aux communication and link training, the host use mailbox to communicate with the ucpu. The dclk pin_pol of vop must not be invert for DP. Signed-off-by: Chris Zhong <zyw@rock-chips.com> [seanpaul fixed up some races between the worker and modeset] [seanpaul squashed ~15 commits from chromium.org gerrit] Signed-off-by: Sean Paul <seanpaul@chromium.org> [groeck fixed compilation errors when building as module] Signed-off-by: Guenter Roeck <groeck@chromium.org>
2017-02-05drm/rockchip: return ERR_PTR instead of NULLJulia Lawall1-1/+1
rockchip_drm_framebuffer_init is only used in one case, in rockchip_drm_fbdev.c, where its return value is tested using IS_ERR. To enable propagating the reason for the error, change the definition so that it returns an ERR_PTR value. Problem found with the help of Coccinelle. Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr>
2017-02-05drm/rockchip: vop: make vop register setting take effectChris Zhong1-0/+4
The setting of vop registers need a reg_done writing to take effect. In vop_enable the vop return to work by by restoring registers, but the registers do not take effect immediately, it should a vop_cfg_done after it. The same thing is needed by windows_disabled in vop_crtc_disable. Signed-off-by: Chris Zhong <zyw@rock-chips.com>
2017-02-03drm: kselftest for drm_mm and bottom-up allocationChris Wilson2-0/+101
Check that if we request bottom-up allocation from drm_mm_insert_node() we receive the next available hole from the bottom. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Link: http://patchwork.freedesktop.org/patch/msgid/20170202114434.3060-2-chris@chris-wilson.co.uk
2017-02-03drm: Improve drm_mm search (and fix topdown allocation) with rbtreesChris Wilson23-442/+470
The drm_mm range manager claimed to support top-down insertion, but it was neither searching for the top-most hole that could fit the allocation request nor fitting the request to the hole correctly. In order to search the range efficiently, we create a secondary index for the holes using either their size or their address. This index allows us to find the smallest hole or the hole at the bottom or top of the range efficiently, whilst keeping the hole stack to rapidly service evictions. v2: Search for holes both high and low. Rename flags to mode. v3: Discover rb_entry_safe() and use it! v4: Kerneldoc for enum drm_mm_insert_mode. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: "Christian König" <christian.koenig@amd.com> Cc: David Airlie <airlied@linux.ie> Cc: Russell King <rmk+kernel@armlinux.org.uk> Cc: Daniel Vetter <daniel.vetter@intel.com> Cc: Jani Nikula <jani.nikula@linux.intel.com> Cc: Sean Paul <seanpaul@chromium.org> Cc: Lucas Stach <l.stach@pengutronix.de> Cc: Christian Gmeiner <christian.gmeiner@gmail.com> Cc: Rob Clark <robdclark@gmail.com> Cc: Thierry Reding <thierry.reding@gmail.com> Cc: Stephen Warren <swarren@wwwdotorg.org> Cc: Alexandre Courbot <gnurou@gmail.com> Cc: Eric Anholt <eric@anholt.net> Cc: Sinclair Yeh <syeh@vmware.com> Cc: Thomas Hellstrom <thellstrom@vmware.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Sinclair Yeh <syeh@vmware.com> # vmwgfx Reviewed-by: Lucas Stach <l.stach@pengutronix.de> #etnaviv Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Link: http://patchwork.freedesktop.org/patch/msgid/20170202210438.28702-1-chris@chris-wilson.co.uk
2017-02-03Merge remote-tracking branch 'airlied/drm-next' into drm-misc-nextDaniel Vetter14-123/+329
Yet another backmerge to get at latest etnaviv code, which is need for Chris' drm_mm patch. Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-20 05:11:31 +0000