diff options
Diffstat (limited to 'tools/perf/pmu-events/arch/x86/knightslanding/frontend.json')
| -rw-r--r-- | tools/perf/pmu-events/arch/x86/knightslanding/frontend.json | 34 |
1 files changed, 34 insertions, 0 deletions
diff --git a/tools/perf/pmu-events/arch/x86/knightslanding/frontend.json b/tools/perf/pmu-events/arch/x86/knightslanding/frontend.json new file mode 100644 index 000000000000..6d38636689a4 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/knightslanding/frontend.json @@ -0,0 +1,34 @@ +[ + { + "EventCode": "0x80", + "Counter": "0,1", + "UMask": "0x3", + "EventName": "ICACHE.ACCESSES", + "SampleAfterValue": "200003", + "BriefDescription": "Counts all instruction fetches, including uncacheable fetches." + }, + { + "EventCode": "0x80", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "ICACHE.HIT", + "SampleAfterValue": "200003", + "BriefDescription": "Counts all instruction fetches that hit the instruction cache." + }, + { + "EventCode": "0x80", + "Counter": "0,1", + "UMask": "0x2", + "EventName": "ICACHE.MISSES", + "SampleAfterValue": "200003", + "BriefDescription": "Counts all instruction fetches that miss the instruction cache or produce memory requests. An instruction fetch miss is counted only once and not once for every cycle it is outstanding." + }, + { + "EventCode": "0xE7", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "MS_DECODED.MS_ENTRY", + "SampleAfterValue": "200003", + "BriefDescription": "Counts the number of times the MSROM starts a flow of uops." + } +]
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