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authorYakir Yang <ykk@rock-chips.com>2016-02-15 19:10:04 +0800
committerYakir Yang <ykk@rock-chips.com>2016-04-05 10:13:02 +0800
commit40fc7ce7db770e9e05032be5eefc183690afb5b8 (patch)
tree4aeb92aaa804f3e2f4dbb64bb1a9b6d9dc12175b /kernel/tsacct.c
parentbcbb7033acf9cea100fb9ea6cd9ff5a7a279d16a (diff)
drm: bridge: analogix/dp: remove duplicate configuration of link rate and link count
link_rate and lane_count already configured in analogix_dp_set_link_train(), so we don't need to config those repeatly after training finished, just remove them out. Beside Display Port 1.2 already support 5.4Gbps link rate, the maximum sets would change from {1.62Gbps, 2.7Gbps} to {1.62Gbps, 2.7Gbps, 5.4Gbps}. Tested-by: Caesar Wang <wxt@rock-chips.com> Tested-by: Douglas Anderson <dianders@chromium.org> Tested-by: Heiko Stuebner <heiko@sntech.de> Tested-by: Javier Martinez Canillas <javier@osg.samsung.com> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Diffstat (limited to 'kernel/tsacct.c')
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