diff options
| author | Yang Yingliang <yangyingliang@huawei.com> | 2022-12-29 17:29:46 +0800 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2023-03-14 17:53:11 -0700 |
| commit | f1d97a37f975ac615e4d6875c27516150642d499 (patch) | |
| tree | 03760d10ec73ac1296c481ad32937a2faf0e2ada /drivers/clk/mediatek | |
| parent | d02fddf24f984b977633c56e10653a8ff19e8c7b (diff) | |
clk: mediatek: clk-pllfh: fix missing of_node_put() in fhctl_parse_dt()
The device_node pointer returned by of_find_compatible_node() with
refcount incremented, when finish using it, the refcount need be
decreased.
Fixes: d7964de8a8ea ("clk: mediatek: Add new clock driver to handle FHCTL hardware")
Signed-off-by: Yang Yingliang <yangyingliang@huawei.com>
Link: https://lore.kernel.org/r/20221229092946.4162345-1-yangyingliang@huawei.com
[sboyd@kernel.org: Also unmap on error]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk/mediatek')
| -rw-r--r-- | drivers/clk/mediatek/clk-pllfh.c | 11 |
1 files changed, 9 insertions, 2 deletions
diff --git a/drivers/clk/mediatek/clk-pllfh.c b/drivers/clk/mediatek/clk-pllfh.c index f48780bec507..f135b32c6dbe 100644 --- a/drivers/clk/mediatek/clk-pllfh.c +++ b/drivers/clk/mediatek/clk-pllfh.c @@ -75,13 +75,13 @@ void fhctl_parse_dt(const u8 *compatible_node, struct mtk_pllfh_data *pllfhs, base = of_iomap(node, 0); if (!base) { pr_err("%s(): ioremap failed\n", __func__); - return; + goto out_node_put; } num_clocks = of_clk_get_parent_count(node); if (!num_clocks) { pr_err("%s(): failed to get clocks property\n", __func__); - return; + goto err; } for (i = 0; i < num_clocks; i++) { @@ -102,6 +102,13 @@ void fhctl_parse_dt(const u8 *compatible_node, struct mtk_pllfh_data *pllfhs, pllfh->state.ssc_rate = ssc_rate; pllfh->state.base = base; } + +out_node_put: + of_node_put(node); + return; +err: + iounmap(base); + goto out_node_put; } static void pllfh_init(struct mtk_fh *fh, struct mtk_pllfh_data *pllfh_data) |