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authorAtish Patra <atish.patra@wdc.com>2020-03-02 15:11:46 -0800
committerMarc Zyngier <maz@kernel.org>2020-03-16 15:48:54 +0000
commitf1ad1133b18f2aed3f6923cdb62b63da230accfd (patch)
treecf9e1ec4b703927faf658de5a123b77632a4d898 /crypto
parentccbe80bad571c2f967ad42b25bbb3ef7a4a24705 (diff)
irqchip/sifive-plic: Add support for multiple PLICs
Current, PLIC driver can support only 1 PLIC on the board. However, there can be multiple PLICs present on a two socket systems in RISC-V. Modify the driver so that each PLIC handler can have a information about individual PLIC registers and an irqdomain associated with it. Tested on two socket RISC-V system based on VCU118 FPGA connected via OmniXtend protocol. Signed-off-by: Atish Patra <atish.patra@wdc.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20200302231146.15530-3-atish.patra@wdc.com
Diffstat (limited to 'crypto')
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