summaryrefslogtreecommitdiff
AgeCommit message (Expand)AuthorFilesLines
2014-05-20drm/i915/chv: Use RMW to toggle swing calc initVille Syrjälä3-7/+35
2014-05-20drm/i915/chv: Don't do group access reads from TX lanes eitherVille Syrjälä3-29/+59
2014-05-20drm/i915/chv: Don't use PCS group access readsVille Syrjälä3-16/+62
2014-05-20drm/i915/chv: Set soft reset override bit for data lane resetsVille Syrjälä3-0/+17
2014-05-20drm/i915/chv: Reset data lanes in encoder .post_disable() hookVille Syrjälä3-6/+48
2014-05-20drm/i915/chv: Turn off dclkp after the PLL has been disabledVille Syrjälä1-5/+10
2014-05-20drm/i915/chv: Move data lane deassert to encoder pre_enableVille Syrjälä3-7/+15
2014-05-20drm/i915/chv: Fix CHV PLL state trackingVille Syrjälä1-15/+26
2014-05-20drm/i915/chv: Register port D encoders and connectorsVille Syrjälä2-0/+10
2014-05-20drm/i915/chv: Fix PORT_TO_PIPE for CHVVille Syrjälä3-0/+6
2014-05-20drm/i915/chv: Bump num_pipes to 3Ville Syrjälä1-1/+1
2014-05-20drm/i915/chv: Add cursor pipe offsetsVille Syrjälä5-45/+71
2014-05-20drm/i915/chv: Fix gmbus for port DVille Syrjälä2-1/+5
2014-05-20drm/i915/chv: Configure crtc_mask correctly for CHVVille Syrjälä2-2/+16
2014-05-20drm/i915/chv: Make CHV irq handler loop until all interrupts are consumedVille Syrjälä1-15/+14
2014-05-20drrm/i915/chv: Use valleyview_pipestat_irq_handler() for CHVVille Syrjälä1-73/+17
2014-05-20drm/i915/chv: Clarify VLV/CHV PIPESTAT bits a bit moreVille Syrjälä1-2/+8
2014-05-20drm/i915/chv: Add CHV display supportRafael Barbalho2-3/+20
2014-05-20drm/i915/chv: Implement WaDisableSamplerPowerBypass for CHVRafael Barbalho1-0/+4
2014-05-20drm/i915/chv: Add some workaround notesVille Syrjälä2-2/+2
2014-05-20drm/i915/chv: Implement WaDisableSDEUnitClockGating:chvVille Syrjälä1-0/+4
2014-05-20drm/i915/chv: Implement WaDisableCSUnitClockGating:chvVille Syrjälä1-0/+4
2014-05-20drm/i915/chv: Implement WaDisableSemaphoreAndSyncFlipWait:chvVille Syrjälä1-0/+4
2014-05-20drm/i915/chv: Implement WaVSRefCountFullforceMissDisable:chv and WaDSRefCount...Ville Syrjälä1-0/+6
2014-05-20drm/i915/chv: Implement WaDisableThreadStallDopClockGating:chvVille Syrjälä1-0/+4
2014-05-20drm/i915/chv: Implement WaDisablePartialInstShootdown:chvVille Syrjälä1-0/+4
2014-05-20drm/i915: s/ironlake_/intel_ for the enable_share_dpll functionDaniel Vetter1-5/+3
2014-05-20drm/i915: Extract intel_prepare_shared_dpllDaniel Vetter1-7/+19
2014-05-20drm/i915: Only update shared dpll state when neededDaniel Vetter1-3/+5
2014-05-20drm/i915: Extract vlv_prepare_pllDaniel Vetter1-23/+30
2014-05-20drm/i915: Extract i9xx_set_pll_dividersDaniel Vetter1-5/+11
2014-05-20drm/i915: Shovel hw setup code out of hsw_crtc_mode_setDaniel Vetter1-23/+24
2014-05-20drm/i915: Shovel hw setup code out of ilk_crtc_mode_setDaniel Vetter1-22/+24
2014-05-20drm/i915: Move lowfreq_avail around a bit in ilk/hsw_crtc_mode_setDaniel Vetter1-5/+5
2014-05-20drm/i915: Shovel hw setup code out of i9xx_crtc_mode_setDaniel Vetter1-35/+63
2014-05-20drm/i915: Implement an oom-notifier for last resort shrinkingChris Wilson2-3/+72
2014-05-20drm/i915: Fix ILK GPU reset domain bitsVille Syrjälä2-7/+13
2014-05-20drm/i915: Fix ILK reset waitVille Syrjälä1-2/+4
2014-05-20drm/i915: Drop bogus comments about display resetVille Syrjälä1-2/+0
2014-05-20drm/i915: Invalidate our pages under memory pressureChris Wilson1-11/+27
2014-05-20drm/i915: Refactor common lock handling between shrinker count/scanChris Wilson1-20/+22
2014-05-20drm/i915: Include bound and active pages in the count of shrinkable objectsChris Wilson3-23/+29
2014-05-20drm/i915: Translate ENOSPC from shmem_get_page() to ENOMEMChris Wilson1-1/+13
2014-05-19drm/i915: Add MIPI mmio reg baseShashank Sharma3-0/+12
2014-05-19drm/i915: Don't die in wait_for_pending_flipsDaniel Vetter1-2/+3
2014-05-19drm/i915: vlv/chv: fix DSI sideband register accessingImre Deak1-2/+2
2014-05-19drm/i915: rename IOSF sideband opcodes according to the specImre Deak2-26/+30
2014-05-19drivers/gpu/drm/i915/intel_display: coding style fixesRobin Schroer1-10/+8
2014-05-19drm/i915: Move fb pinning into __intel_set_modeDaniel Vetter1-60/+20
2014-05-19drm/i915: Inline set_base into crtc_mode_setDaniel Vetter1-6/+63
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-27 18:24:01 +0000