diff options
| author | Topi Pohjolainen <topi.pohjolainen@intel.com> | 2017-11-23 17:19:06 +0200 |
|---|---|---|
| committer | Topi Pohjolainen <topi.pohjolainen@intel.com> | 2018-01-10 12:33:49 +0200 |
| commit | e77b7fac31dc0a6dcc573e5aaf6a0f054e0c1955 (patch) | |
| tree | bdb9e8db1cd17b3384b8a797bf96799529a88bcb | |
| parent | 0f4fdfd05b12d75e25c8efb7565c5e1a9adff840 (diff) | |
intel/compiler: Prepare for 16-bit 3-src ops
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
| -rw-r--r-- | src/intel/compiler/brw_eu_emit.c | 21 | ||||
| -rw-r--r-- | src/intel/compiler/brw_inst.h | 4 | ||||
| -rw-r--r-- | src/intel/compiler/brw_reg_type.c | 2 |
3 files changed, 27 insertions, 0 deletions
diff --git a/src/intel/compiler/brw_eu_emit.c b/src/intel/compiler/brw_eu_emit.c index 3b9bf08c73..983c90f0c5 100644 --- a/src/intel/compiler/brw_eu_emit.c +++ b/src/intel/compiler/brw_eu_emit.c @@ -810,6 +810,7 @@ brw_alu3(struct brw_codegen *p, unsigned opcode, struct brw_reg dest, assert(dest.file == BRW_GENERAL_REGISTER_FILE || dest.file == BRW_MESSAGE_REGISTER_FILE); assert(dest.type == BRW_REGISTER_TYPE_F || + dest.type == BRW_REGISTER_TYPE_HF || dest.type == BRW_REGISTER_TYPE_DF || dest.type == BRW_REGISTER_TYPE_D || dest.type == BRW_REGISTER_TYPE_UD); @@ -857,6 +858,21 @@ brw_alu3(struct brw_codegen *p, unsigned opcode, struct brw_reg dest, */ brw_inst_set_3src_a16_src_type(devinfo, inst, dest.type); brw_inst_set_3src_a16_dst_type(devinfo, inst, dest.type); + + if (dest.type == BRW_REGISTER_TYPE_HF) { + /* From the Bspec: Instruction types + * + * Three source instructions can use operands with mixed-mode + * precision. When SrcType field is set to :f or :hf it defines + * precision for source 0 only, and fields Src1Type and Src2Type + * define precision for other source operands: + * + * 0b = :f. Single precision Float (32-bit). + * 1b = :hf. Half precision Float (16-bit). + */ + brw_inst_set_3src_src1_type(devinfo, inst, 1); + brw_inst_set_3src_src2_type(devinfo, inst, 1); + } } } @@ -902,11 +918,16 @@ brw_inst *brw_##OP(struct brw_codegen *p, \ struct brw_reg src2) \ { \ assert(dest.type == BRW_REGISTER_TYPE_F || \ + dest.type == BRW_REGISTER_TYPE_HF || \ dest.type == BRW_REGISTER_TYPE_DF); \ if (dest.type == BRW_REGISTER_TYPE_F) { \ assert(src0.type == BRW_REGISTER_TYPE_F); \ assert(src1.type == BRW_REGISTER_TYPE_F); \ assert(src2.type == BRW_REGISTER_TYPE_F); \ + } else if (dest.type == BRW_REGISTER_TYPE_HF) { \ + assert(src0.type == BRW_REGISTER_TYPE_HF); \ + assert(src1.type == BRW_REGISTER_TYPE_HF); \ + assert(src2.type == BRW_REGISTER_TYPE_HF); \ } else if (dest.type == BRW_REGISTER_TYPE_DF) { \ assert(src0.type == BRW_REGISTER_TYPE_DF); \ assert(src1.type == BRW_REGISTER_TYPE_DF); \ diff --git a/src/intel/compiler/brw_inst.h b/src/intel/compiler/brw_inst.h index 2501d6adff..c295a2b3ff 100644 --- a/src/intel/compiler/brw_inst.h +++ b/src/intel/compiler/brw_inst.h @@ -222,6 +222,10 @@ F8(3src_src1_negate, 39, 39, 40, 40) F8(3src_src1_abs, 38, 38, 39, 39) F8(3src_src0_negate, 37, 37, 38, 38) F8(3src_src0_abs, 36, 36, 37, 37) + +F(3src_src2_type, 36, 36) +F(3src_src1_type, 35, 35) + F8(3src_a16_flag_reg_nr, 34, 34, 33, 33) F8(3src_a16_flag_subreg_nr, 33, 33, 32, 32) FF(3src_a16_dst_reg_file, diff --git a/src/intel/compiler/brw_reg_type.c b/src/intel/compiler/brw_reg_type.c index b7fff0867f..55956ef563 100644 --- a/src/intel/compiler/brw_reg_type.c +++ b/src/intel/compiler/brw_reg_type.c @@ -93,6 +93,7 @@ enum hw_3src_reg_type { GEN7_3SRC_TYPE_D = 1, GEN7_3SRC_TYPE_UD = 2, GEN7_3SRC_TYPE_DF = 3, + GEN7_3SRC_TYPE_HF = 4, /** When ExecutionDatatype is 1: @{ */ GEN10_ALIGN1_3SRC_REG_TYPE_HF = 0b000, @@ -120,6 +121,7 @@ static const struct hw_3src_type { [BRW_REGISTER_TYPE_D] = { GEN7_3SRC_TYPE_D }, [BRW_REGISTER_TYPE_UD] = { GEN7_3SRC_TYPE_UD }, [BRW_REGISTER_TYPE_DF] = { GEN7_3SRC_TYPE_DF }, + [BRW_REGISTER_TYPE_HF] = { GEN7_3SRC_TYPE_HF }, }, gen10_hw_3src_align1_type[] = { #define E(x) BRW_ALIGN1_3SRC_EXEC_TYPE_##x [0 ... BRW_REGISTER_TYPE_LAST] = { INVALID }, |