From 632c245c3bfdfd2fd9d32e4ea162ef716b2e3de8 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Tue, 10 Aug 2010 10:07:16 +1000 Subject: evergreen: add initial support using code from DDX --- avivotool.c | 96 +++++++++++++++++++++++++++++++++++++++++++++++++++--------- radeon.h | 1 + radeon_reg.h | 32 ++++++++++++++++++++ 3 files changed, 115 insertions(+), 14 deletions(-) diff --git a/avivotool.c b/avivotool.c index dd819a7..88b74f9 100644 --- a/avivotool.c +++ b/avivotool.c @@ -716,7 +716,7 @@ int get_mask(int num_bits) } void __attribute__((__sentinel__(0))) -radeon_show_reg_bits(const char *name, unsigned long index_addr, +radeon_show_reg_bits(const char *prefix, const char *name, unsigned long index_addr, unsigned long data_addr, unsigned long addr, ...) { va_list ap; @@ -730,7 +730,7 @@ radeon_show_reg_bits(const char *name, unsigned long index_addr, else value = radeon_get(addr, name); - printf("%s\t%08x\n", name, value); + printf("%s%s\t%08x\n", prefix ? prefix : "", name, value); va_start(ap, addr); while (1) { @@ -915,19 +915,84 @@ const char *get_reg_name(unsigned long address, const char *type) return NULL; } -void radeon_cmd_regs(const char *type) +#define GET_REG(r) radeon_get(r, #r) +#define SHOW_REG(r) printf("%s\t%08x\n", #r, radeon_get(r, #r)) +#define SHOW_UNKNOWN_REG(r) { tmp = radeon_get(r, "byhand"); printf("%08lx\t%08x (%d)\n", r, tmp, tmp); } +#define REG_TYPE_NAME(r) ((r == REG_TYPE_STATIC) ? "static" : ((r == REG_TYPE_SEMI_STATIC) ? "semi-static" : "random")) +#define SHOW_STATIC_REG(r) { tmp = get_reg_type(r); printf("%s (%08lx)\t%s\n", get_reg_name(r, ""), r, REG_TYPE_NAME(tmp)); } +#define SHOW_REG_DECIMAL(r) printf("%s\t%d (decimal)\n", #r, radeon_get(r, #r)) +#define SHOW_REG_BITS(r, ...) radeon_show_reg_bits(NULL, #r, 0, 0, r, __VA_ARGS__) +#define SHOW_MC_REG(r) printf("%s\t%08x\n", #r, radeon_get_indexed(AVIVO_MC_INDEX, AVIVO_MC_DATA, (r | 0x007f0000), #r)) +#define SHOW_MC_REG_BITS(r, ...) radeon_show_reg_bits(NULL, AVIVO_MC_INDEX, AVIVO_MC_DATA, #r, (r | 0x007f0000), __VA_ARGS__) +#define SHOW_PCIE_REG(r) printf("%s\t%08x\n", #r, radeon_get_indexed(0x30, 0x34, (r), #r)) + +static uint32_t eg_offsets[] = { EVERGREEN_CRTC0_REGISTER_OFFSET, EVERGREEN_CRTC1_REGISTER_OFFSET, + EVERGREEN_CRTC2_REGISTER_OFFSET, EVERGREEN_CRTC3_REGISTER_OFFSET, + EVERGREEN_CRTC4_REGISTER_OFFSET, EVERGREEN_CRTC5_REGISTER_OFFSET }; + +#define EG_NUM_OFFSETS (sizeof(eg_offsets) / sizeof(eg_offsets[0])) +void eg_cmd_regs(const char *type) { - #define GET_REG(r) radeon_get(r, #r) - #define SHOW_REG(r) printf("%s\t%08x\n", #r, radeon_get(r, #r)) - #define SHOW_UNKNOWN_REG(r) { tmp = radeon_get(r, "byhand"); printf("%08lx\t%08x (%d)\n", r, tmp, tmp); } - #define REG_TYPE_NAME(r) ((r == REG_TYPE_STATIC) ? "static" : ((r == REG_TYPE_SEMI_STATIC) ? "semi-static" : "random")) - #define SHOW_STATIC_REG(r) { tmp = get_reg_type(r); printf("%s (%08lx)\t%s\n", get_reg_name(r, ""), r, REG_TYPE_NAME(tmp)); } - #define SHOW_REG_DECIMAL(r) printf("%s\t%d (decimal)\n", #r, radeon_get(r, #r)) - #define SHOW_REG_BITS(r, ...) radeon_show_reg_bits(#r, 0, 0, r, __VA_ARGS__) - #define SHOW_MC_REG(r) printf("%s\t%08x\n", #r, radeon_get_indexed(AVIVO_MC_INDEX, AVIVO_MC_DATA, (r | 0x007f0000), #r)) - #define SHOW_MC_REG_BITS(r, ...) radeon_show_reg_bits(AVIVO_MC_INDEX, AVIVO_MC_DATA, #r, (r | 0x007f0000), __VA_ARGS__) - #define SHOW_PCIE_REG(r) printf("%s\t%08x\n", #r, radeon_get_indexed(0x30, 0x34, (r), #r)) + int show_grphs = 0; + int i; + uint32_t tmp, tmp1; + + for (i = 0; i < EG_NUM_OFFSETS; i++) { + tmp = GET_REG(EVERGREEN_CRTC_CONTROL + eg_offsets[i]); + if (tmp & 0x1) + show_grphs |= (1 << i); + + printf("D%dCRTC: %s\n", i+1, tmp & 0x1 ? "Enabled" : "Disabled"); + if (!(tmp & 0x1)) + continue; + + tmp = GET_REG(EVERGREEN_VIEWPORT_START + eg_offsets[i]); + tmp1 = GET_REG(EVERGREEN_VIEWPORT_SIZE + eg_offsets[i]); + printf("Viewport start x: %d y: %d, w %d h %d\n", tmp >> 16, tmp & 0xffff, + tmp1 >> 16, tmp1 & 0xffff); + + } + + for (i = 0; i < EG_NUM_OFFSETS; i++) { + char grphname[10]; + if (!(show_grphs & (1 << i))) + continue; + + snprintf(grphname, 10, "D%dGRPH", i+1); + tmp = GET_REG(EVERGREEN_GRPH_ENABLE + eg_offsets[i]); + if (!(tmp & 0x1)) { + printf("\n%s: disabled\n", grphname, i); + continue; + } + printf("\n%s: enabled %08x, control %08x\n", grphname, tmp, + GET_REG(EVERGREEN_GRPH_CONTROL + eg_offsets[i])); + radeon_show_reg_bits(grphname, "CONTROL", 0, 0, + EVERGREEN_GRPH_CONTROL + eg_offsets[i], + 0, 1, "Depth", + 8, 10, "Format", + 0, 0, NULL); + printf("pitch %08x\n", + GET_REG(EVERGREEN_GRPH_PITCH + eg_offsets[i])); + printf("Primary surface address %08x:%08x\n", + GET_REG(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + eg_offsets[i]), + GET_REG(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + eg_offsets[i])); + printf("Secondary surface address %08x:%08x\n", + GET_REG(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + eg_offsets[i]), + GET_REG(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + eg_offsets[i])); + printf("Surface offset X %08x Y %08x\n", + GET_REG(EVERGREEN_GRPH_SURFACE_OFFSET_X + eg_offsets[i]), + GET_REG(EVERGREEN_GRPH_SURFACE_OFFSET_Y + eg_offsets[i])); + printf("X/Y start %08x %08x, end %08x %08x\n", + GET_REG(EVERGREEN_GRPH_X_START + eg_offsets[i]), + GET_REG(EVERGREEN_GRPH_Y_START + eg_offsets[i]), + GET_REG(EVERGREEN_GRPH_X_END + eg_offsets[i]), + GET_REG(EVERGREEN_GRPH_Y_END + eg_offsets[i])); + } + printf("\n"); +} +void radeon_cmd_regs(const char *type) +{ int show_all = (strcmp(type, "all") == 0); int show_core = (show_all || strstr(type, "core")); int show_mc = (show_all || strstr(type, "mc")); @@ -2095,7 +2160,10 @@ int main(int argc, char *argv[]) return 0; } if (strcmp(argv[1], "regs") == 0) { - radeon_cmd_regs("default"); + if (IS_EG(card_info)) + eg_cmd_regs("default"); + else + radeon_cmd_regs("default"); return 0; } if (strcmp(argv[1], "i2c") == 0) { diff --git a/radeon.h b/radeon.h index 7ca52d8..7deaa9e 100644 --- a/radeon.h +++ b/radeon.h @@ -77,3 +77,4 @@ typedef struct { #include "radeon_chipinfo_gen.h" #define IS_RV620(card_info) (card_info && card_info->chip_family >= CHIP_FAMILY_RV620) +#define IS_EG(card_info) (card_info && card_info->chip_family >= CHIP_FAMILY_CEDAR) diff --git a/radeon_reg.h b/radeon_reg.h index c9b634b..9432be9 100644 --- a/radeon_reg.h +++ b/radeon_reg.h @@ -3034,3 +3034,35 @@ #define RADEON_MC_DEBUG 0x188 #endif +/* GRPH blocks at 0x6800, 0x7400, 0x10000, 0x10c00, 0x11800, 0x12400 */ +#define EVERGREEN_GRPH_ENABLE 0x6800 +#define EVERGREEN_GRPH_CONTROL 0x6804 +#define EVERGREEN_GRPH_SWAP_CONTROL 0x680c +#define EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS 0x6810 +#define EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS 0x6814 +#define EVERGREEN_GRPH_PITCH 0x6818 +#define EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x681c +#define EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x6820 +#define EVERGREEN_GRPH_SURFACE_OFFSET_X 0x6824 +#define EVERGREEN_GRPH_SURFACE_OFFSET_Y 0x6828 +#define EVERGREEN_GRPH_X_START 0x682c +#define EVERGREEN_GRPH_Y_START 0x6830 +#define EVERGREEN_GRPH_X_END 0x6834 +#define EVERGREEN_GRPH_Y_END 0x6838 + +/* CUR blocks at 0x6998, 0x7598, 0x10198, 0x10d98, 0x11998, 0x12598 */ +#define EVERGREEN_CUR_CONTROL 0x6998 + +/* display controller offsets used for crtc/cur/lut/grph/viewport/etc. */ +#define EVERGREEN_CRTC0_REGISTER_OFFSET (0x6df0 - 0x6df0) +#define EVERGREEN_CRTC1_REGISTER_OFFSET (0x79f0 - 0x6df0) +#define EVERGREEN_CRTC2_REGISTER_OFFSET (0x105f0 - 0x6df0) +#define EVERGREEN_CRTC3_REGISTER_OFFSET (0x111f0 - 0x6df0) +#define EVERGREEN_CRTC4_REGISTER_OFFSET (0x11df0 - 0x6df0) +#define EVERGREEN_CRTC5_REGISTER_OFFSET (0x129f0 - 0x6df0) + +#define EVERGREEN_VIEWPORT_START 0x6d70 +#define EVERGREEN_VIEWPORT_SIZE 0x6d74 + +/* CRTC blocks at 0x6df0, 0x79f0, 0x105f0, 0x111f0, 0x11df0, 0x129f0 */ +#define EVERGREEN_CRTC_CONTROL 0x6e70 -- cgit v1.2.3