radeonbios: add some more combios tables

1 files changed, 160 insertions, 50 deletions

diff --git a/radeontool.c b/radeontool.c
index 51406fb..2e88109 100644
--- a/radeontool.c
+++ b/radeontool.c
@@ -1256,8 +1256,28 @@ static void radeon_rom_legacy_lcdtable(unsigned char *bios, int hdr)
 
 	extended_offset = BIOS16(offset+0x26);
 	if (extended_offset) {
-	    printf("lcd panel extended info offset: %d\n", extended_offset);
-	    printf("lcd extended info rev: %d\n", BIOS8(extended_offset));
+		int extended_rev = BIOS8(extended_offset);
+		printf("lcd panel extended info offset: %x\n", extended_offset);
+		printf("lcd extended info rev: %x\n", extended_rev);
+		
+		printf("SS delay %x step size %x\n", BIOS8(extended_offset+1),
+		       BIOS8(extended_offset + 2));
+
+		if (extended_rev > 1) {
+			printf("lcd fake edid id num  bytes %d\n", BIOS8(extended_offset+3));
+			printf("lcd fake edid id num offset 0x%x\n", BIOS16(extended_offset+4));
+		}
+		if (extended_rev > 2) {
+			printf("lcd LVPVS %x\n", BIOS8(extended_offset+6));
+			printf("lcd PVG/PCP %x\n", BIOS8(extended_offset+7));
+			printf("lcd SSPLL table offset %x\n", BIOS16(extended_offset+8));
+		}
+		if (extended_rev > 3) {
+			printf("lcd resp time coeff 0x%x\n", BIOS8(extended_offset+10));
+		}
+		if (extended_rev > 4) {
+			printf("edid low refresh offset 0x%x\n", BIOS16(extended_offset+11));
+		}
 	}
 
 	printf("lcd panel vcc delay: %d\n", BIOS16(offset+0x2c));
@@ -2002,59 +2022,145 @@ static void radeon_rom_legacy_miscinfotable(unsigned char *bios, int hdr)
     }
 }
 
-static void radeon_rom_legacy_dynclk1table(unsigned char *bios, int hdr)
+static void radeon_rom_legacy_mmio_table(unsigned char *bios, int offset)
 {
-    int offset, type, start, i = 0;
+	if (!offset)
+		return;
 
-    offset = BIOS16(hdr + 0x52);
-    if (offset == 0) {
-	printf("No dyn clock 1 info table\n");
-	return;
-    }
-    start = BIOS8(offset);
-    printf("dyn clock 1 info table\n");
-    while (start != 0) {
-	type = (start & 0xc0) >> 6;
-	if (type == 0) {
-	    int reg = BIOS8(offset + i) & 0x3f;
-	    unsigned int val = BIOS32(offset + i + 1);
-	    printf("pll reg: 0x%x, val: 0x%x\n", reg, val);
-		i += 5;
-	} else if (type == 1) {
-	    int reg = BIOS8(offset + i) & 0x3f;
-	    int byte_offset = BIOS8(offset + i + 1);
-	    int and_mask = BIOS8(offset + i + 2);
-	    int or_mask  = BIOS8(offset + i + 3);
-	    printf("pll reg: 0x%x, byte offset of dword 0x%x, AND mask: 0x%x, OR mask: 0x%x\n",
-		   reg, byte_offset, and_mask, or_mask);
-	    i += 4;
-	} else if (type >= 2) {
-	    int cmd = BIOS8(offset + i) & 0x3f;
-	    switch (cmd) {
-	    case 1:
-		printf("delay 150 us\n");
-		    break;
-	    case 2:
-		printf("delay 1 ms\n");
-		break;
-	    case 3:
-		printf("wait for MC_BUSY = 0 in CLK_PWRMGT_CNTL\n");
-		break;
-	    case 4:
-		printf("wait for DLL_READY = 1 in CLK_PWRMGT_CNTL\n");
-		break;
+	while (BIOS16(offset)) {
+		uint16_t cmd = (BIOS16(offset) & 0xe000) >> 13;
+		uint32_t addr = BIOS16(offset) & 0x1fff;
+		uint32_t val, and_mask, or_mask, tmp;
+
+		offset+=2;
+		switch(cmd) {
+		case 0:
+		case 1:
+			val = BIOS32(offset);
+			offset += 4;
+			printf("write reg %x %x\n", addr, val);
+			break;
+		case 2:
+		case 3:
+			and_mask = BIOS32(offset);
+			offset += 4;
+			or_mask = BIOS32(offset);
+			offset += 4;
+			printf("write reg %x and %x or %x val\n",
+			       addr, and_mask, or_mask);
+			break;
+		case 4:
+			val = BIOS16(offset);
+			offset += 2;
+			printf("delay %x\n", val);
+			break;
 		case 5:
-		    printf("check and set bit 24 in CLK_PWRMGT_CNTL to 0\n");
-		    break;
-	    }
-	    i += 1;
-	} else
-	    break;
-	start = BIOS8(offset + i);
-    }
-    
+			val = BIOS16(offset);
+			offset += 2;
+			switch (addr) {
+			case 8:
+				printf("wait for CLK_PWRMGR CNTL MC busy %x\n", val);
+				break;
+			case 9:
+				printf("wait for MC_STATUS MC idle %x\n", val);
+				break;
+			}
+			break;
+		default:
+			printf("unknown\n");
+		}
+	}
 }
 
+
+static void radeon_rom_legacy_asicinittable(unsigned char *bios, int hdr)
+{
+	int offset = BIOS16(hdr + 0xc);
+	if (offset) {
+		printf("asic init table 1\n");
+		radeon_rom_legacy_mmio_table(bios, offset);
+	}
+
+	offset = BIOS16(hdr + 0x4e);
+	if (offset) {
+		printf("-----------------\n");
+		printf("asic init table 2\n");
+		radeon_rom_legacy_mmio_table(bios, offset);
+	}
+}
+
+static void radeon_rom_legacy_plltable(unsigned char *bios, int offset)
+{
+	int type, start, i = 0;
+	start = BIOS8(offset);
+	while (start != 0) {
+		type = (start & 0xc0) >> 6;
+		if (type == 0) {
+			int reg = BIOS8(offset + i) & 0x3f;
+			unsigned int val = BIOS32(offset + i + 1);
+			printf("pll reg: 0x%x, val: 0x%x\n", reg, val);
+			i += 5;
+		} else if (type == 1) {
+			int reg = BIOS8(offset + i) & 0x3f;
+			int byte_offset = BIOS8(offset + i + 1);
+			int and_mask = BIOS8(offset + i + 2);
+			int or_mask  = BIOS8(offset + i + 3);
+			printf("pll reg: 0x%x, byte offset of dword 0x%x, AND mask: 0x%x, OR mask: 0x%x\n",
+			       reg, byte_offset, and_mask, or_mask);
+			i += 4;
+		} else if (type >= 2) {
+			int cmd = BIOS8(offset + i) & 0x3f;
+			switch (cmd) {
+			case 1:
+				printf("delay 150 us\n");
+				break;
+			case 2:
+				printf("delay 1 ms\n");
+				break;
+			case 3:
+				printf("wait for MC_BUSY = 0 in CLK_PWRMGT_CNTL\n");
+				break;
+			case 4:
+				printf("wait for DLL_READY = 1 in CLK_PWRMGT_CNTL\n");
+				break;
+			case 5:
+				printf("check and set bit 24 in CLK_PWRMGT_CNTL to 0\n");
+				break;
+			default:
+				printf("ass\n");
+				break;
+			}
+			i += 1;
+		} else
+			break;
+		start = BIOS8(offset + i);
+	}
+}
+
+static void radeon_rom_legacy_dynclk1table(unsigned char *bios, int hdr)
+{
+	int offset, type, start, i = 0;
+
+	offset = BIOS16(hdr + 0x52);
+	if (offset == 0) {
+		printf("No dyn clock 1 info table\n");
+		return;
+	}
+	printf("dyn clock 1 info table\n");
+	radeon_rom_legacy_plltable(bios, offset);
+}
+
+static void radeon_rom_legacy_pllinittable(unsigned char *bios, int hdr)
+{
+	int offset, type, start, i = 0;
+
+	offset = BIOS16(hdr + 0x46);
+	if (offset == 0) {
+		return;
+	}
+	printf("pll init table\n");
+	radeon_rom_legacy_plltable(bios, offset);
+}
 static void radeon_rom_legacy_dynclk2table(unsigned char *bios, int hdr)
 {
     int offset, type, start, rev, i = 0;
@@ -2458,6 +2564,10 @@ void radeon_rom_tables(const char * file)
 		printf("BIOS Rev: %x.%x\n\n", BIOS8(hdr+4), BIOS8(hdr+5));
 		radeon_rom_legacy_list_tables_present(bios, hdr);
 		printf("-------------\n");
+		radeon_rom_legacy_asicinittable(bios, hdr);
+		printf("-------------\n");
+		radeon_rom_legacy_pllinittable(bios, hdr);
+		printf("-------------\n");
 		radeon_rom_legacy_clocks(bios, hdr);
 		printf("-------------\n");
 		radeon_rom_legacy_connectors(bios, hdr);