radeonreg: add radeonreg regs all option

detect the chip family and dump appropriately.

Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

2 files changed, 107 insertions, 40 deletions

diff --git a/radeon.h b/radeon.h
index 0289e01..b8aa8f1 100644
--- a/radeon.h
+++ b/radeon.h
@@ -7,11 +7,12 @@ static char *family_strings[] = {"Unknown", "legacy", "radeon",
 				 "rs480", "rv515", "r520", "rv530", "r580",
 				 "rv560", "rv570", "rs600", "rs690", "rs740",
 				 "r600", "r630", "rv610", "rv630", "rv670",
-				 "rv620", "rv635", "rs780", "rs880", 
-				"rv770", "rv730", "rv710", "rv740",
-				"cedar", "redwood", "juniper",
-				"cypress", "hemlock" };
-			  
+				 "rv620", "rv635", "rs780", "rs880",
+				 "rv770", "rv730", "rv710", "rv740",
+				 "cedar", "redwood", "juniper",
+				 "cypress", "hemlock",
+				 "palm",
+				 "barts", "turks", "caicos" };
 
 typedef enum {
     CHIP_FAMILY_UNKNOW,
@@ -20,8 +21,7 @@ typedef enum {
     CHIP_FAMILY_RV100,
     CHIP_FAMILY_RS100,    /* U1 (IGP320M) or A3 (IGP320)*/
     CHIP_FAMILY_RV200,
-    CHIP_FAMILY_RS200,    /* U2 (IGP330M/340M/350M) or A4 (IGP330/340/345/350), 
-RS250 (IGP 7000) */
+    CHIP_FAMILY_RS200,    /* U2 (IGP330M/340M/350M) or A4 (IGP330/340/345/350), RS250 (IGP 7000) */
     CHIP_FAMILY_R200,
     CHIP_FAMILY_RV250,
     CHIP_FAMILY_RS300,    /* RS300/RS350 */
@@ -82,3 +82,19 @@ typedef struct {
 
 #define IS_RV620(card_info) (card_info && card_info->chip_family >= CHIP_FAMILY_RV620)
 #define IS_EG(card_info) (card_info && card_info->chip_family >= CHIP_FAMILY_CEDAR)
+
+#define IS_DISPLAY_RADEON(card_info) (card_info && \
+				      (card_info->chip_family >= CHIP_FAMILY_RADEON) && \
+				      (card_info->chip_family <= CHIP_FAMILY_RS480))
+#define IS_DISPLAY_AVIVO(card_info) (card_info && \
+				     (card_info->chip_family >= CHIP_FAMILY_RV515) && \
+				     (card_info->chip_family <= CHIP_FAMILY_RV670))
+#define IS_DISPLAY_DCE3(card_info) (card_info && \
+				    (card_info->chip_family >= CHIP_FAMILY_RV620) && \
+				    (card_info->chip_family <= CHIP_FAMILY_RV740))
+#define IS_DISPLAY_DCE4(card_info) (card_info && \
+				    (card_info->chip_family >= CHIP_FAMILY_CEDAR) && \
+				    (card_info->chip_family <= CHIP_FAMILY_PALM))
+#define IS_DISPLAY_DCE5(card_info) (card_info && \
+				    (card_info->chip_family >= CHIP_FAMILY_BARTS) && \
+				    (card_info->chip_family <= CHIP_FAMILY_CAICOS))
diff --git a/radeonreg.c b/radeonreg.c
index d9fc471..9948665 100644
--- a/radeonreg.c
+++ b/radeonreg.c
@@ -180,61 +180,112 @@ static void usage(void)
 
 #define SHOW_UNK_CLK_REG(r) printf("%02x\t%08x\n", r, radeon_get_indexed(RADEON_CLOCK_CNTL_INDEX, RADEON_CLOCK_CNTL_DATA, (r), #r))
 
-void radeon_cmd_regs(const char *type)
+static void radeon_show_radeon_display_regs(const char *type)
 {
-    int show_all = (strcmp(type, "all") == 0);
-    int shut_up = 1;
     int tmp; /* may be stomped at any moment. */
     unsigned long i;
 
-    /* Dump all registers that we can read. */
-    if (strcmp(type, "radeon") == 0) {
-        for (i = 0x0000; i < 0x00fc; i += 4)
+    for (i = 0x0000; i < 0x00fc; i += 4)
+            SHOW_UNKNOWN_REG(i);
+    for (i = 0x0200; i < 0x060c; i += 4)
+            SHOW_UNKNOWN_REG(i);
+    for (i = 0x0800; i < 0x0904; i += 4)
+            SHOW_UNKNOWN_REG(i);
+    for (i = 0x0d00; i < 0x0d78; i += 4)
+            SHOW_UNKNOWN_REG(i);
+    for (i = 0; i < 0x2f; i++)
+	    SHOW_UNK_CLK_REG(i);
+}
+
+static void radeon_show_avivo_display_regs(const char *type)
+{
+    int tmp; /* may be stomped at any moment. */
+    unsigned long i;
+
+    for (i = 0x0000; i < 0x5b4; i += 4)
+            SHOW_UNKNOWN_REG(i);
+    for (i = 0x5dfc; i < 0x7ff0; i += 4)
             SHOW_UNKNOWN_REG(i);
-        for (i = 0x0200; i < 0x060c; i += 4)
+    for (i = 0; i < 0x3f; i++)
+	    SHOW_UNK_CLK_REG(i);
+}
+
+static void radeon_show_dce3_display_regs(const char *type)
+{
+    int tmp; /* may be stomped at any moment. */
+    unsigned long i;
+
+    for (i = 0x0000; i < 0x5bc; i += 4)
+            SHOW_UNKNOWN_REG(i);
+    for (i = 0x5dfc; i < 0x8000; i += 4)
+            SHOW_UNKNOWN_REG(i);
+}
+
+static void radeon_show_dce4_display_regs(const char *type)
+{
+    int tmp; /* may be stomped at any moment. */
+    unsigned long i;
+
+    for (i = 0x0000; i < 0x5e8; i += 4)
             SHOW_UNKNOWN_REG(i);
-        for (i = 0x0800; i < 0x0904; i += 4)
+    for (i = 0x5c6c; i < 0x7f64; i += 4)
             SHOW_UNKNOWN_REG(i);
-        for (i = 0x0d00; i < 0x0d78; i += 4)
+    for (i = 0x10000; i < 0x12f64; i += 4)
             SHOW_UNKNOWN_REG(i);
-	for (i = 0; i < 0x2f; i++)
-        	SHOW_UNK_CLK_REG(i);
+}
+
+static void radeon_show_dce5_display_regs(const char *type)
+{
+    int tmp; /* may be stomped at any moment. */
+    unsigned long i;
+
+    for (i = 0x0000; i < 0x5e8; i += 4)
+            SHOW_UNKNOWN_REG(i);
+    for (i = 0x5800; i < 0x7fa4; i += 4)
+            SHOW_UNKNOWN_REG(i);
+    for (i = 0x10000; i < 0x12fa4; i += 4)
+            SHOW_UNKNOWN_REG(i);
+}
+
+void radeon_cmd_regs(const char *type)
+{
+
+    /* Dump all registers that we can read. */
+    if (strcmp(type, "radeon") == 0) {
+	radeon_show_radeon_display_regs(type);
         return;
     }
     if (strcmp(type, "avivo") == 0) {
-        for (i = 0x0000; i < 0x5b4; i += 4)
-            SHOW_UNKNOWN_REG(i);
-        for (i = 0x5dfc; i < 0x7ff0; i += 4)
-            SHOW_UNKNOWN_REG(i);
-	for (i = 0; i < 0x3f; i++)
-        	SHOW_UNK_CLK_REG(i);
+	radeon_show_avivo_display_regs(type);
         return;
     }
     if (strcmp(type, "dce3") == 0) {
-        for (i = 0x0000; i < 0x5bc; i += 4)
-            SHOW_UNKNOWN_REG(i);
-        for (i = 0x5dfc; i < 0x8000; i += 4)
-            SHOW_UNKNOWN_REG(i);
+	radeon_show_dce3_display_regs(type);
         return;
     }
     if (strcmp(type, "dce4") == 0) {
-        for (i = 0x0000; i < 0x5e8; i += 4)
-            SHOW_UNKNOWN_REG(i);
-        for (i = 0x5c6c; i < 0x7f64; i += 4)
-            SHOW_UNKNOWN_REG(i);
-        for (i = 0x10000; i < 0x12f64; i += 4)
-            SHOW_UNKNOWN_REG(i);
+	radeon_show_dce4_display_regs(type);
         return;
     }
     if (strcmp(type, "dce5") == 0) {
-        for (i = 0x0000; i < 0x5e8; i += 4)
-            SHOW_UNKNOWN_REG(i);
-        for (i = 0x5800; i < 0x7fa4; i += 4)
-            SHOW_UNKNOWN_REG(i);
-        for (i = 0x10000; i < 0x12fa4; i += 4)
-            SHOW_UNKNOWN_REG(i);
+	radeon_show_dce5_display_regs(type);
         return;
     }
+    if (strcmp(type, "all") == 0) {
+	    if (IS_DISPLAY_RADEON(card_info))
+		    radeon_show_radeon_display_regs(type);
+	    else if (IS_DISPLAY_AVIVO(card_info))
+		    radeon_show_avivo_display_regs(type);
+	    else if (IS_DISPLAY_DCE3(card_info))
+		    radeon_show_dce3_display_regs(type);
+	    else if (IS_DISPLAY_DCE4(card_info))
+		    radeon_show_dce4_display_regs(type);
+	    else if (IS_DISPLAY_DCE5(card_info))
+		    radeon_show_dce5_display_regs(type);
+	    else
+		    printf("unknown chipset, specify the regs to dump\n");
+	    return;
+    }
 }
 
 void radeon_reg_match(const char *pattern)